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Axcelerator Family FPGAs
ue
TM
Leading-Edge Performance
* * * * * * * * * 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded FIFOs 700 Mb/s LVDS Capable I/Os Up to 2 Million Equivalent System Gates Up to 684 I/Os Up to 10,752 Dedicated Flip-Flops Up to 295 kbits Embedded SRAM/FIFO Manufactured on Advanced 0.15 m CMOS Antifuse Process Technology, 7 Layers of Metal Single-Chip, Nonvolatile Solution Up to 100% Resource Utilization with 100% Pin Locking 1.5V Core Voltage for Low Power Footprint Compatible Packaging Flexible, Multi-Standard I/Os: - 1.5V, 1.8V, 2.5V, 3.3V Mixed Voltage Operation - Bank-Selectable I/Os - 8 Banks per Chip - Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V PCI, and 3.3V PCI-X - Differential I/O Standards: LVPECL and LVDS
AX125 125,000 82,000 672 1,344 1,344 4 18,432 4 4 8 8 168 84 504 180
Specifications
*
Features
* * * * *
* *
* * * *
Voltage-Referenced I/O Standards: GTL+, HSTL Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2 - Registered I/Os - Hot-Swap Compliant I/Os (except PCI) - Programmable Slew Rate and Drive Strength on Outputs - Programmable Delay and Weak Pull-Up/Pull-Down Circuits on Inputs Embedded Memory: - Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4, x9, x18, x36 Organizations Available) - Independent, Width-Configurable Read and Write Ports - Programmable Embedded FIFO Control Logic Segmentable Clock Resources Embedded Phase-Locked Loop: - 14-200 MHz Input Range - Frequency Synthesis Capabilities up to 1 GHz Deterministic, User-Controllable Timing Unique In-System Diagnostic and Debug Capability with Actel Silicon Explorer II Boundary-Scan Testing Compliant with IEEE Standard 1149.1 (JTAG) FuseLock TM Secure Programming Technology Prevents Reverse Engineering and Design Theft
-
Table 1-1 * Axcelerator Family Product Profile Device Capacity (in Equivalent System Gates) Typical Gates Modules Register (R-cells) Combinatorial (C-cells) Maximum Flip-Flops Embedded RAM/FIFO Number of Core RAM Blocks Total Bits of Core RAM Clocks (Segmentable) Hardwired Routed PLLs I/Os I/O Banks Maximum User I/Os Maximum LVDS Channels Total I/O Registers Package CSP PQFP BGA FBGA CQFP CCGA
AX250 250,000 154,000 1,408 2,816 2,816 12 55,296 4 4 8 8 248 124 744
AX500 500,000 286,000 2,688 5,376 5,376 16 73,728 4 4 8 8 336 168 1,008
AX1000 1,000,000 612,000 6,048 12,096 12,096 36 165,888 4 4 8 8 516 258 1,548
AX2000 2,000,000 1,060,000 10,752 21,504 21,504 64 294,912 4 4 8 8 684 342 2,052
208 256, 324 256, 484 208, 352
208 484, 676 208, 352 729 484, 676, 896 352 624 896, 1152 352 624
November 2008 (c) 2008 Actel Corporation
i *See Actel's website for the latest version of the datasheet.
Axcelerator Family FPGAs
Ordering Information
AX1000 _ 1 FG G 896 I Application Blank = Commercial (0 to +70 C) PP = Pre-Production I = Industrial (-40 to +85 C) M = Military (-55 to +125 C) B = MIL-STD-883 Class B Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant Packaging Package Type BG = Ball Grid Array (1.27mm pitch) FG = Fine Ball Grid Array (1.0mm pitch) CS = Chip Scale Package (0.8mm pitch) PQ = Plastic Quad Flat Pack (0.5mm pitch) CQ = Ceramic Quad Flat Pack (0.5mm pitch) CG = Ceramic Column Grid Array Speed Grade Blank = Standard Speed 1 = Approximately 15% Faster than Standard 2 = Approximately 25% Faster than Standard Part Number AX125 = 125,000 Equivalent System Gates AX250 = 250,000 Equivalent System Gates AX500 = 500,000 Equivalent System Gates AX1000 = 1,000,000 Equivalent System Gates AX2000 = 2,000,000 Equivalent System Gates
Device Resources
User I/Os (Including Clock Buffers) Package CS180 PQ208 CQ208 FG256 FG324 CQ352 FG484 CG624 FG676 BG729 FG896 FG1152 AX125 98 - - 138 168 - - - - - - - AX250 - 115 115 138 - 198 248 - - - - - AX500 - 115 115 - - 198 317 - 336 - - - AX1000 - - - - - 198 317 418 418 516 516 - AX2000 - - - - - 198 - 418 - - 586 684
Note: The FG256, FG324, and FG484 are footprint compatible with one another. The FG676, FG896, and FG1152 are also footprint compatible with one another.
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Temperature Grade Offerings
Package CS180 PQ208 CQ208 FG256 FG324 CQ352 FG484 CG624 FG676 BG729 FG896 FG1152 Notes: 1. 2. 3. 4. C = Commercial I = Industrial M = Military B = MIL-STD-883 Class B AX125 C, I - - C, I C, I - - - - - - - AX250 - C, I, M M, B C, I, M - M, B C, I, M - - - - - AX500 - C, I, M M, B - - M, B C, I, M - C, I, M - - - AX1000 - - - - - M, B C, I, M M, B C, I, M C, I, M C, I, M - AX2000 - - - - - M, B - M, B - - C, I, M C, I, M
Speed Grade and Temperature Grade Matrix
Std C I M B Notes: 5. 6. 7. 8. C = Commercial I = Industrial M = Military B = MIL-STD-883 Class B -1 -2 - -
Packaging Data
Refer to the following documents located on the Actel website for additional packaging information. Package Mechanical Drawings Package Thermal Characteristics and Weights Hermatic Package Mechanical Information Contact your local Actel representative for device availability.
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Table of Contents
General Description
Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Programmable Interconnect Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Low Power (LP) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 In-System Diagnostic and Debug Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Detailed Specifications
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Voltage-Referenced I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 Differential Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 Module Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 Routing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 Global Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55 Axcelerator Clock Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72 Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-89 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91
Package Pin Assignments
180-Pin CSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 729-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 324-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
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1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-78 208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-83 352-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-88 624-Pin CCGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-102
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
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Axcelerator Family FPGAs
General Description
Axcelerator offers high performance at densities of up to two million equivalent system gates. Based upon the Actel AX architecture, Axcelerator has several systemlevel features such as embedded SRAM (with complete FIFO control logic), PLLs, segmentable clocks, chip-wide highway routing, and carry logic. page 1-2). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on traditional FPGAs) and enables the efficient sea-of-modules architecture. The antifuses are normally open circuit and, when programmed, form a permanent, passive, lowimpedance connection, leading to the fastest signal propagation in the industry. In addition, the extremely small size of these interconnect elements gives the Axcelerator family abundant routing resources. The very nature of Actel's nonvolatile antifuse technology provides excellent protection against design pirating and cloning (FuseLock technology). Cloning is impossible (even if the security fuse is left unprogrammed) as no bitstream or programming file is ever downloaded or stored in the device. Reverse engineering is virtually impossible due to the difficulty of trying to distinguish between programmed and unprogrammed antifuses and also due to the programming methodology of antifuse devices (see "Security" on page 2-90).
Device Architecture
Actel's AX architecture, derived from the highlysuccessful SX-A sea-of-modules architecture, has been designed for high performance and total logic module utilization (Figure 1-1). Unlike in traditional FPGAs, the entire floor of the Axcelerator device is covered with a grid of logic modules, with virtually no chip area lost to interconnect elements or routing.
Programmable Interconnect Element
The Axcelerator family uses a patented metal-to-metal antifuse programmable interconnect element that resides between the upper two layers of metal (Figure 1-2 on
Routing
Switch Matrix Logic Block
Sea-of-Modules Architecture Traditional FPGA Architecture
Logic Modules
Figure 1-1 * Sea-of-Modules Comparison
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Axcelerator Family FPGAs
Figure 1-2 * Axcelerator Family Interconnect Elements
Logic Modules
Actel's Axcelerator family provides two types of logic modules: the register cell (R-cell) and the combinatorial cell (C-cell). The can implement more than 4,000 combinatorial functions of up to five inputs (Figure 1-3 on page 1-3). The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and active-low enable control signals (Figure 1-3 on page 1-3). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility (e.g., easy mapping of dual-data-rate functions into the FPGA) while conserving valuable clock resources. The clock source for the R-cell can be chosen from the hardwired clocks, routed clocks, or internal logic. Two C-cells, a single R-cell, and two Transmit (TX) and two Receive (RX) routing buffers form a Cluster, while two Clusters comprise a SuperCluster (Figure 1-4 on page 1-3). Each SuperCluster also contains an independent Buffer (B) module, which supports buffer insertion on high-fanout nets by the place-and-route tool, minimizing system delays while improving logic utilization. The logic modules within the SuperCluster are arranged so that two combinatorial modules are side-by-side, giving a C-C-R - C-C-R pattern to the SuperCluster. This C-C-R pattern enables efficient implementation (minimum delay) of two-bit carry logic for improved arithmetic performance (Figure 1-5 on page 1-3). The AX architecture is fully fracturable, meaning that if one or more of the logic modules in a SuperCluster are used by a particular signal path, the other logic modules are still available for use by other paths. At the chip level, SuperClusters are organized into core tiles, which are arrayed to build up the full chip. For example, the AX1000 is composed of a 3x3 array of nine core tiles. Surrounding the array of core tiles are blocks of I/O Clusters and the I/O bank ring (Table 1-1 on page 1-3). Each core tile consists of an array of 336 SuperClusters and four SRAM blocks (176 SuperClusters and three SRAM blocks for the AX250). The SRAM blocks are arranged in a column on the west side of the tile (Figure 1-6 on page 1-4).
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FCI
A[1:0] B[1:0] D[3:0] DB CFN C-cell Y
D E CLK
PSET CLR
Q
(Positive Edge Triggered) FCO
C-Cell
Figure 1-3 * AX C-Cell and R-Cell
R-Cell
C
C
R
TX RX
TX RX B
TX RX
TX RX
C
C
R
Figure 1-4 * AX SuperCluster
FCI
DCOUT C-Cell Y C-Cell Y
Carry Logic FCO
Figure 1-5 * AX 2-bit Carry Logic Table 1-1 * Number of Core Tiles per Device Device AX125 AX250 AX500 AX1000 AX2000 Number of Core Tiles 1 regular tile 4 smaller tiles 4 regular tiles 9 regular tiles 16 regular tiles
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Axcelerator Family FPGAs
SuperCluster
C
C
R
TX RX
TX RX B
TX RX
TX RX
C
C
R
RAMC
SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC
SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC
SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC
SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC
SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC
SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC
RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD RD
SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC
SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC
SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC
SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC
SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC
SC SC SC SC SC SC SC SC SC SC SC SC SC SC HD SC SC SC SC SC SC SC SC SC SC SC SC SC SC
4k RAM/ FIFO 4k RAM/ FIFO
RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC HD RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC RAMC
Chip Layout
4k RAM/ FIFO 4k RAM/ FIFO
SC SC CoreSCTile
I/O Structure See Figure 7
Figure 1-6 * AX Device Architecture (AX1000 shown)
Embedded Memory
As mentioned earlier, each core tile has either three (in a smaller tile) or four (in the regular tile) embedded SRAM blocks along the west side, and each variable-aspectratio SRAM block is 4,608 bits in size. Available memory configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or 4kx1 bits. The individual blocks have separate read and write ports that can be configured with different bit widths on each port. For example, data can be written in by eight and read out by one. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using core logic modules. The FIFO width and depth are programmable. The FIFO also features programmable ALMOST-EMPTY (AEMPTY) and ALMOST-FULL (AFULL) flags in addition to the normal EMPTY and FULL flags. In addition to the flag logic, the embedded FIFO control unit also contains the counters necessary for the generation of the read and write address pointers as well
as control circuitry to prevent metastability and erroneous operation. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
I/O Logic
The Axcelerator family of FPGAs features a flexible I/O structure, supporting a range of mixed voltages with its bank-selectable I/Os: 1.5V, 1.8V, 2.5V, and 3.3V. In all, Axcelerator FPGAs support at least 14 different I/O standards (single-ended, differential, voltage-referenced). The I/Os are organized into banks, with eight banks per device (two per side). The configuration of these banks determines the I/O standards supported (see "User I/Os" on page 2-10 for more information). All I/O standards are available in each bank. Each I/O module has an input register (InReg), an output register (OutReg), and an enable register (EnReg) (Figure 1-7 on page 1-5). An I/O Cluster includes two I/O modules, four RX modules, two TX modules, and a buffer (B) module.
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I/O Module
InReg
OutReg
EnReg
I O B A N K
4k RAM/ FIFO
I/O Module
4k RAM/ FIFO
TX RX RX B
TX RX RX
I/O Module
I/O Cluster
4k RAM/ FIFO
CoreTile
4k RAM/ FIFO
Figure 1-7 * I/O Cluster Arrangement
Routing
The AX hierarchical routing structure ties the logic modules, the embedded memory blocks, and the I/O modules together (Figure 1-8 on page 1-6). At the lowest level, in and between SuperClusters, there are three local routing structures: FastConnect, DirectConnect, and CarryConnect routing. DirectConnects provide the highest performance routing inside the SuperClusters by connecting a C-cell to the adjacent R-cell. DirectConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns. FastConnects provide high-performance, horizontal routing inside the SuperCluster and vertical routing to the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering a maximum routing delay of 0.4 ns. CarryConnects are used for routing carry logic between adjacent SuperClusters. They connect the FCO output of one two-bit, C-cell carry logic to the FCI input of the twobit, C-cell carry logic of the SuperCluster below it. CarryConnects do not require an antifuse to make the connection and achieve a signal propagation time of less than 0.1 ns.
The next level contains the core tile routing. Over the SuperClusters within a core tile, both vertical and horizontal tracks run across rows or columns, respectively. At the chip level, vertical and horizontal tracks extend across the full length of the device, both north-to-south and east-to-west. These tracks are composed of highway routing that extend the entire length of the device (segmented at core tile boundaries) as well as segmented routing of varying lengths.
Global Resources
Each family member has three types of global signals available to the designer: HCLK, CLK, and GCLR/GPSET. There are four hardwired clocks (HCLK) per device that can directly drive the clock input of each R-cell. Each of the four routed clocks (CLK) can drive the clock, clear, preset, or enable pin of an R-cell or any input of a C-cell (Figure 1-3 on page 1-3). Global clear (GCLR) and global preset (GPSET) drive the clear and preset inputs of each R-cell as well as each I/O Register on a chip-wide basis at power-up. Each HCLK and CLK has an associated analog PLL (a total of eight per chip). Each embedded PLL can be used for clock delay minimization, clock delay adjustment, or clock frequency synthesis. The PLL is capable of
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Axcelerator Family FPGAs
Figure 1-8 * AX Routing Structures
operating with input frequencies ranging from 14 MHz to 200 MHz and can generate output frequencies between 20 MHz and 1 GHz. The clock can be either divided or multiplied by factors ranging from 1 to 64. Additionally, multiply and divide settings can be used in any combination as long as the resulting clock frequency is between 20 MHz and 1 GHz. Adjacent PLLs can be cascaded to create complex frequency combinations. The PLL can be used to introduce either a positive or a negative clock delay of up to 3.75 ns in 250 ps increments. The reference clock required to drive the PLL can be derived from three sources: external input pad (either single-ended or differential), internal logic, or the output of an adjacent PLL.
Design Environment
The Axcelerator family of FPGAs is fully supported by both Actel's LiberoTM Integrated Design Environment and Designer FPGA Development software. Actel Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see the Libero IDE Flow diagram located on Actel's website). Libero IDE includes Synplify(R) Actel Edition (AE) from Synplicity(R), ViewDraw(R) AE from Mentor Graphics(R), ModelSim(R) HDL Simulator from Mentor Graphics, WaveFormer LiteTM AE from SynaptiCAD(R), and Designer software from Actel. Actel's Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes the following: * Timer - a world-class integrated static timing analyzer and constraints editor which support timing-driven place-and-route NetlistViewer - a design netlist schematic viewer ChipPlanner - a graphical floorplanner viewer and editor SmartPower - allows the designer to quickly estimate the power consumption of a design PinEditor - a graphical application for editing pin assignments and I/O attributes I/O Attribute Editor - displays all assigned and unassigned I/O macros and their attributes in a spreadsheet format
Low Power (LP) Mode
The AX architecture was created for high-performance designs but also includes a low power mode (activated via the LP pin). When the low power mode is activated, I/O banks can be disabled (inputs disabled, outputs tristated), and PLLs can be placed in a power-down mode. All internal register states are maintained in this mode. Furthermore, individual I/O banks can be configured to opt out of the LP mode, thereby giving the designer access to critical signals while the rest of the chip is in low power mode. The power can be further reduced by providing an external voltage source (VPUMP) to the device to bypass the internal charge pump (See "Low Power Mode" on page 2-89 for more information).
* * * * *
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With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, Actel's back-annotation flow is compatible with all the major simulators and the simulation results can be cross-probed with Silicon Explorer II, Actel's integrated verification and logic analysis tool. Another tool included in the Designer software is the SmartGen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems.
In-System Diagnostic and Debug Capabilities
The Axcelerator family of FPGAs includes internal probe circuitry, allowing the designer to dynamically observe and analyze any signal inside the FPGA without disturbing normal device operation. Up to four individual signals can be brought out to dedicated probe pins (PRA/B/C/D) on the device. The probe circuitry is accessed and controlled via Silicon Explorer II (Figure 1-9), Actel's integrated verification and logic analysis tool that attaches to the serial port of a PC and communicates with the FPGA via the JTAG port (See "Silicon Explorer II Probe Interface" on page 2-91).
Summary Programming
Programming support is provided through Actel's Silicon Sculptor II, a single-site programmer driven via a PCbased GUI. In addition, BP Microsystems offers multi-site programmers that provide qualified support for Actel devices. Factory programming is available for highvolume production needs. Actel's Axcelerator family of FPGAs extends the successful SX-A architecture, adding embedded RAM/ FIFOs, PLLs, and high-speed I/Os. With the support of a suite of robust software tools, design engineers can incorporate high gate counts and fixed pins into an Axcelerator design yet still achieve high performance and efficient device utilization.
16 Pin Connection TDI TCK
Axcelerator FPGAs
Serial Connection
Silicon Explorer II
TMS TDO PRA PRB
22 Pin Connection CH3/PRC CH4/PRD Additional 14 Channels (Logic Analyzer)
Figure 1-9 * Probe Setup
v2.7
1-7
Axcelerator Family FPGAs
Related Documents
Application Notes
Simultaneous Switching Noise and Signal Integrity http://www.actel.com/documents/SSN_AN.pdf Axcelerator Family PLL and Clock Management http://www.actel.com/documents/AX_PLL_AN.pdf Implementing DDR Transmit in Axcelerator http://www.actel.com/documents/AX_DDR_AN.pdf Implementation of Security in Actel Antifuse FPGAs http://www.actel.com/documents/Antifuse_Security_AN.pdf
User's Guides and Manuals
Antifuse Macro Library Guide http://www.actel.com/documents/libguide_UG.pdf SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder http://www.actel.com/documents/genguide_ug.pdf Silicon Sculptor II User's Guide http://www.actel.com/techdocs/manuals/default.asp
White Paper
Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.actel.com/documents/DesignSecurity_WP.pdf Understanding Actel Antifuse Device Security http://www.actel.com/documents/AntifuseSecurity_WP.pdf
Miscellaneous
Libero IDE flow diagram http://www.actel.com/products/tools/libero/flow.html
1 -8
v2.7
Axcelerator Family FPGAs
Detailed Specifications
Operating Conditions
Table 2-1 lists the absolute maximum ratings of Axcelerator devices. Stresses beyond the ratings may cause permanent damage to the device. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the recommendations in Table 2-2.
Table 2-1 * Absolute Maximum Ratings Symbol VCCA VCCI VREF VI VO TSTG VCCDA* Parameter DC Core Supply Voltage DC I/O Supply Voltage DC I/O Reference Voltage Input Voltage Output Voltage Storage Temperature Supply Voltage for Differential I/Os Limits -0.3 to 1.6 -0.3 to 3.75 -0.3 to 3.75 -0.5 to 3.75 -0.5 to 3.75 -60 to +150 -0.3 to 3.75 Units V V V V V C V
Note: * Should be the maximum of all VCCI. Table 2-2 * Recommended Operating Conditions Commercial 0 to +70 1.425 to 1.575 1.425 to 1.575 1.71 to 1.89 2.375 to 2.625 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 Industrial -40 to +85 1.425 to 1.575 1.425 to 1.575 1.71 to 1.89 2.375 to 2.625 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 Military -55 to +125 1.425 to 1.575 1.425 to 1.575 1.71 to 1.89 2.375 to 2.625 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 Units C V V V V V V V
Parameter Range Ambient Temperature (TA)1 1.5V Core Supply Voltage 1.5V I/O Supply Voltage 1.8V I/O Supply Voltage 2.5V I/O Supply Voltage 3.3V I/O Supply Voltage VCCDA Supply Voltage VPUMP Supply Voltage Notes:
1. Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used for military grades. 2. TJ max = 125C
Power-Up/Down Sequence
All Axcelerator I/Os are tristated during power-up until normal device operating conditions are reached, when I/Os enter user mode. VCCDA should be powered up before (or coincidentally with) VCCA and VCCI to ensure the behavior of user I/Os at system start-up. Conversely, VCCDA should be powered down after (or coincidentally with) VCCA and VCCI. Note that VCCI and VCCA can be powered up in any sequence with respect to each other, provided the requirement with respect to VCCDA is satisfied.
v2.7
2-1
Axcelerator Family FPGAs
Calculating Power Dissipation
Table 2-3 * Standby Current ICCA ICCDA ICCBANK ICCPLL Standby Current per PLL 0.2 1 1 2 0.2 1 1 2 0.2 1 1 1.5 0.2 1 1 1.5 0.2 1 1 1.5 ICCCP Standby Current, Charge Pump Active 0.3 0.4 0.4 0.4 0.3 0.4 0.4 0.4 0.3 0.4 0.4 0.4 0.3 0.4 0.4 0.4 0.3 0.4 0.4 0.4 Bypassed Mode Units 0.01 0.01 0.2 0.5 0.01 0.01 0.2 0.5 0.01 0.01 0.2 0.5 0.01 0.01 0.2 0.5 0.01 0.01 0.2 0.5 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Standby Current per Standby I/O Bank Standby Current, Current Differential (Core) I/O 2.5V VCCI 3.3V VCCI 1.5 15 25 50 1.5 30 40 70 5 60 80 180 7.5 80 120 200 20 160 200 500 1.5 6 6 8 1.4 7 7 9 1.4 7 7 9 1.5 8 8 10 1.6 10 10 15 0.2 0.5 0.6 1 0.25 0.8 0.8 1.3 0.4 1 1 1.75 0.5 1.5 1.5 3 0.7 2 3 4 0.3 0.75 0.8 1.5 0.4 0.9 1 1.8 0.75 1.5 1.9 2.5 1.25 3 3.4 4 1.5 7 8 10
Device AX125
Temperature Typical at 25C 70C 85C 125C
AX250
Typical at 25C 70C 85C 125C
AX500
Typical at 25C 70C 85C 125C
AX1000
Typical at 25C 70C 85C 125C
AX2000
Typical at 25C 70C 85C 125C
Note: ICCCP Active is the ICCDA or the Internal Charge Pump current. ICCCP Bypassed mode is the External Charge Pump current IIH (VPUMP pin). Table 2-4 * Default CLOAD/VCCI CLOAD (pF) Single-Ended without VREF LVTTL 24mA High Slew LVTTL 16mA High Slew LVTTL 12mA High Slew LVTTL 8mA High Slew LVTTL 24mA Low Slew LVTTL 16mA Low Slew LVTTL 12mA Low Slew LVTTL 8mA Low Slew LVCMOS - 25 LVCMOS - 18 Note: *PI/O = P10 + CLOAD *VCCI2 35 35 35 35 35 35 35 35 35 35 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 2.5 1.8 381.2 381.2 381.2 381.2 381.2 381.2 381.2 381.2 218.8 113.4 262.6 220.1 160.9 125.4 164.2 145.9 133.6 113.8 143.2 68.7 643.7 601.3 542.1 506.5 545.4 527.0 514.8 494.9 361.9 182.1 VCCI (V) PLOAD (w/MHz) P10 (w/MHz) PI/O (W/MHz)*
2 -2
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Axcelerator Family FPGAs
Table 2-4 *
Default CLOAD/VCCI (Continued) CLOAD (pF) VCCI (V) 1.5 3.3 3.3 PLOAD (w/MHz) 78.8 108.9 108.9 P10 (w/MHz) 44.9 213.5 158.0 PI/O (W/MHz)* 123.6 322.4 266.9
LVCMOS - 15 (JESD8-11) PCI PCI-X Single-Ended with VREF HSTL-I SSTL2-I SSTL2-II SSTL3-I SSTL3-II GTLP - 25 GTLP - 33 Differential LVPECL - 33 LVDS - 25 Note: *PI/O = P10 + Table 2-5 * CLOAD *VCCI2
35 10 10
20 30 30 30 30 10 10
1.5 2.5 2.5 3.3 3.3 2.5 3.3
-
36.8 166.9 143.5 322.8 284.0 TBD TBD
36.8 166.9 143.5 322.8 284.0 TBD TBD
N/A N/A
3.3 2.5
-
255.1 140.4
255.1 140.4
Different Components Contributing to the Total Power Consumption in Axcelerator Devices Device Specific Value (in W/MHz)
Component P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13
Definition Core tile HCLK power component R-cell power component HCLK signal power dissipation Core tile RCLK power component R-cell power component RCLK signal power dissipation Power dissipation due to the switching activity on the R-cell Power dissipation due to the switching activity on the C-cell Power component associated with the input voltage Power component associated with the output voltage Power component associated with the read operation in the RAM block Power component associated with the write operation in the RAM block Core PLL power component
AX125 AX250 AX500 AX1000 33 0.2 4.5 33 0.3 6.5 1.6 1.4 10 49 0.2 4.5 49 0.3 6.5 1.6 1.4 10 71 0.2 9 71 0.3 13 1.6 1.4 10 130 0.2 13.5 130 0.3 19.5 1.6 1.4 10
AX2000 216 0.2 18 216 0.3 26 1.6 1.4 10
See table Per pin contribution 25 30 1.5 25 30 1.5 25 30 1.5 25 30 1.5 25 30 1.5
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Axcelerator Family FPGAs
Ptotal = Pdc + Pac
Pdc Pac = = ICCA * VCCA PHCLK + PCLK + PR-cells + PC-cells + Pinputs + Poutputs + Pmemory + PPLL
PHCLK = (P1 + P2 * s + P3 * sqrt[s]) * Fs
s Fs = the number of R-cells clocked by this clock = the clock frequency
PCLK = (P4 + P5 * s + P6 * sqrt[s]) * Fs
s Fs = the number of R-cells clocked by this clock = the clock frequency
PR-cells = P7 * ms * Fs
ms Fs = = the number of R-cells switching at each Fs cycle the clock frequency
PC-cells = P8 * mc * Fs
mc = the number of C-cells switching at each Fs cycle Fs = the clock frequency
Pinputs = P9 * pi * Fpi
pi Fpi = the number of inputs = the average input frequency
Poutputs = PI/O * po * Fpo
Cload VCCI po Fpo = = = = the output load (technology dependent) the output voltage (technology dependent) the number of outputs the average output frequency
Pmemory = P11 * Nblock * FRCLK + P12 * Nblock * FWCLK
Nblock = the number of RAM/FIFO blocks (1 block = 4k) FRCLK = the read-clock frequency of the memory FWCLK = the write-clock frequency of the memory
PPLL = P13 * FCLK
FRefCLK = the clock frequency of the clock input of the PLL FCLK = the clock frequency of the first clock output of the PLL
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Axcelerator Family FPGAs
Power Estimation Example
This example employs an AX1000 shift-register design with 1,080 R-cells, one C-cell, one reset input, and one LVTTL 12mA Output, with High Slew. This design uses one HCLK at 100 MHz.
ms Fs s = 1,080 (in a shift register - 100% of R-cells are toggling at each clock cycle) = 100 MHz = 1080 => PHCLK = (P1 + P2 * s + P3 * sqrt[s]) * Fs = 79 mW and Fs = 100 MHz => PR-cells = P7 * ms * Fs = 173 mW mc = 1 (1 C-cell in this shift-register) and Fs = 100 MHz => PC-cells = P8 * mc * Fs = 0.14 mW
Fpi ~ 0 MHz and pi= 1 (1 reset input => this is why Fpi=0) => Pinputs = P9 * pi * Fpi = 0 mW Fpo = 50 MHz and po = 1 => Poutputs = PI/O * po * Fpo= 27.10 mW No RAM/FIFO in this shift-register => Pmemory = 0 mW No PLL in this shift-register => PPLL = 0 mW Pac = PHCLK + PCLK + PR-cells + PC-cells + Pinputs + Poutputs + Pmemory + PPLL = 276 mW Pdc = 7.5mA * 1.5V = 11.25 mW Ptotal = Pdc + Pac = 11.25 mW + 276mW = 290.30 mW
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2-5
Axcelerator Family FPGAs
Thermal Characteristics
Introduction
The temperature variable in Actel's Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ 2-1 can be used to calculate junction temperature. TJ = Junction Temperature = T + Ta
EQ 2-1
T = ja * P
EQ 2-2
Where: Ta = Ambient Temperature between junction T = Temperature gradient (silicon) and ambient
Where: P = Power ja = Junction to ambient of package. ja numbers are located under Table 2-6 on page 2-6.
Package Thermal Characteristics
The device junction-to-case thermal characteristic is jc, and the junction-to-ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. jc values are provided for reference. The absolute maximum junction temperature is 125C. The maximum power dissipation allowed for commercial- and industrial-grade devices is a function of ja. A sample calculation of the absolute maximum power dissipation allowed for an 896-pin FBGA package at commercial temperature and still air is as follows:
125C - 70C Max. junction temp. (C) - Max. ambient temp. (C) Maximum Power Allowed = -------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 4.04 W 13.6C/W ja (C/W)
The maximum power dissipation allowed for Military temperature and Mil-Std 883B devices is specified as a function of jc.
Table 2-6 * Package Thermal Characteristics Package Type Chip Scale Package (CSP) Plastic Quad Flat Pack (PQFP) Plastic Ball Grid Array (PBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Fine Pitch Ball Grid Array (FBGA) Ceramic Quad Flat Pack (CQFP) Ceramic Quad Flat Pack
1
Pin Count 180 208 729 256 324 484 676 896 1152 208 352 624
jc N/A 8.0 2.2 3.0 3.0 3.2 3.2 2.4 1.8 2.0 2.0 6.5
ja Still Air 57.8 26 13.7 26.6 25.8 20.5 16.4 13.6 12.0 22 17.9 8.9
ja 1.0m/s 51.0 23.5 10.6 22.8 22.1 17.0 13.0 10.4 8.9 19.8 16.1 8.5
ja 2.5m/s 50 20.9 9.6 21.5 20.9 15.9 12.0 9.4 7.9 18.0 14.7 8
Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W
(CQFP)1
Ceramic Column Grid Array (CCGA)2 Notes:
1. jc for the 208-pin and 352-pin CQFP refers to the thermal resistance between the junction and the bottom of the package. 2. jc for the 624-pin CCGA refers to the thermal resistance between the junction and the top surface of the package. Thermal resistance from junction to board (jb) for CCGA 624 package is 3.4C/W.
2 -6
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Axcelerator Family FPGAs
Timing Characteristics
Axcelerator devices are manufactured in a CMOS process, therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. The derating factors shown in Table 2-7 should be applied to all timing data contained within this datasheet.
Table 2-7 * Temperature and Voltage Timing Derating Factors (Normalized to Worst-Case Commercial, TJ = 70C, VCCA = 1.425V) Junction Temperature VCCA 1.4V 1.425V 1.5V 1.575V 1.6V Notes: 1. The user can set the junction temperature in Designer software to be any integer value in the range of -55C to 175C. 2. The user can set the core voltage in Designer software to be any value between 1.4V and 1.6V. -55C 0.83 0.82 0.78 0.74 0.73 -40C 0.86 0.84 0.80 0.76 0.75 0C 0.91 0.90 0.85 0.81 0.80 25C 0.96 0.94 0.89 0.85 0.84 70C 1.02 1.00 0.95 0.90 0.89 85C 1.05 1.04 0.98 0.94 0.92 125C 1.15 1.13 1.07 1.02 1.01
All timing numbers listed in this datasheet represent sample timing characteristics of Axcelerator devices. Actual timing delay values are design-specific and can be derived from the Timer tool in Actel's Designer software after placeand-route.
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Axcelerator Family FPGAs
Timing Model
I/O Module (Nonregistered) Carry Chain Combinatorial Cell FCO tPDC = 0.57 ns I/O Module (Registered) + tDP = 1.70 ns tRD2 = 0.53 ns Buffer Module tBFPD = 0.12 ns tICKLQ = 0.67 ns tSUD = 0.23 ns Hardwired Clock tHCKH = 3.03 ns FMAX (external) = 350 MHz FMAX (internal) = 870 MHz I/O Module (Non- registered) Combinatorial Cell Y tPD = 0.74 ns tBFPD = 0.12 ns tRD1 = 0.45 ns tRD2 = 0.53 ns tRD3 = 0.56 ns Buffer Module tCCY = 0.61 ns I/O I/O Module (Nonregistered) tPY = 3.03 ns LVTTL Output Drive Strength = 4 (24mA) High Slew Rate Combinatorial Cell tPY = 2.28 ns I/O LVPECL
LVPECL
Register Cell
D
Q
Combinatorial I/O Module Register Cell Cell tOCLKY = 0.67 ns tRCO = 0.67 ns Buffer tRD1 = 0.45 ns tSUD = 0.23 ns tSUD = 0.23 ns Module DQ DQ Y tBPFD = 0.12 ns tPD = 0.74 ns tRCKL = 3.08 ns FMAX (external) = 350 MHz FMAX (internal) = 870 MHz Routed Clock
tPY = 1.01 ns GTL + 3.3V
LVDS
+
tRCO = 0.67 ns tSUD = 0.23 ns
tDP = 1.84 ns
Hardwired or Routed Clock
tHCKL = 3.02 ns tRCKL = 3.08 ns
Note: Worst case timing data for the AX1000, -2 speed grade Figure 2-1 * Worst Case Timing Data
Hardwired Clock - Using LVTTL 24mA High Slew Clock I/O
External Setup = (tDP + tRD2 + tSUD) - tHCKL = (1.72 + 0.53 + 0.23) - 3.02 = -0.54 ns Clock-to-Out (Pad-to-Pad) = tHCKL + tRCO + tRD1 + tPYs = 3.02 + 0.67 + 0.45 + 3.03 = 7.17 ns
Routed Clock - Using LVTTL 24mA High Slew Clock I/O
External Setup = (tDP + tRD2 + tSUD) - tRCKH = (1.72 + 0.53 + 0.23) - 3.13 = -0.65 ns Clock-to-Out (Pad-to-Pad) = tRCKH + tRCO + tRD1 + tPY = 3.13 + 0.67 + 0.45 + 3.03 = 7.28 ns
2 -8
v2.7
Axcelerator Family FPGAs
I/O Specifications
Pin Descriptions
Supply Pins
GND Ground
Axcelerator Chip 250 1.5V Supply 10f 0.1f VCOMPLX VCCPLX
Low supply voltage.
VCCA Supply Voltage
Supply voltage for array (1.5V). See "Operating Conditions" on page 2-1 for more information.
VCCIBx Supply Voltage
Figure 2-2 * VCCPLX and VCOMPLX Power Supply Connect
Supply voltage for I/Os. Bx is the I/O Bank ID - 0 to 7. See "Operating Conditions" on page 2-1 for more information.
VCCDA Supply Voltage
User-Defined Supply Pins
VREF Supply Voltage
Supply voltage for the I/O differential amplifier and JTAG and probe interfaces. See "Operating Conditions" on page 2-1 for more information. VCCDA should be tied to 3.3V.
VCCPLA/B/C/D/E/F/G/H Supply Voltage
Reference voltage for I/O banks. VREF pins are configured by the user from regular I/O pins; VREF pins are not in fixed locations. There can be one or more VREF pins in an I/O bank.
Global Pins
HCLKA/B/C/D Dedicated (Hardwired) Clocks A, B, C and D
PLL analog power supply (1.5V) for internal PLL. There are eight in each device. VCCPLA supports the PLL associated with global resource HCLKA, VCCPLB supports the PLL associated with global resource HCLKB, etc. The PLL analog power supply pins should be connected to 1.5V whether PLL is used or not.
VCOMPLA/B/C/D/E/F/G/HSupply Voltage
Compensation reference signals for internal PLL. There are eight in each device. VCOMPLA supports the PLL associated with global resource HCLKA, VCOMPLE supports the PLL associated with global resource CLKE, etc. (see Figure 2-2 on page 2-9 for correct external connection to the supply). The VCOMPLX pins should be left floating if PLL is not used.
VPUMP Supply Voltage (External Pump)
These pins are the clock inputs for sequential modules or north PLLs. Input levels are compatible with all supported I/O standards. There is a P/N pin pair for support of differential I/O standards. Single-ended clock I/Os can only be assigned to the P side of a paired I/O. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. When the HCLK pins are unused, it is recommended that they are tied to ground.
CLKE/F/G/H Routed Clocks E, F, G, and H
In the low power mode, VPUMP will be used to access an external charge pump (if the user desires to bypass the internal charge pump to further reduce power). The device starts using the external charge pump when the voltage level on VPUMP reaches VIH1. In normal device operation, when using the internal charge pump, VPUMP should be tied to GND.
These pins are clock inputs for clock distribution networks or south PLLs. Input levels are compatible with all supported I/O standards. There is a P/N pin pair for support of differential I/O standards. Single-ended clock I/Os can only be assigned to the P side of a paired I/O. The clock input is buffered prior to clocking the R-cells. When the CLK pins are unused, Actel recommends that they are tied to ground.
1. When VPUMP = VIH, it shuts off the internal charge pump. See "Low Power Mode" on page 2-89.
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Axcelerator Family FPGAs
JTAG/Probe Pins
PRA/B/C/D Probe A/B/C/D
User I/Os2
Introduction
The Axcelerator family features a flexible I/O structure, supporting a range of mixed voltages (1.5V, 1.8V, 2.5V, and 3.3V) with its bank-selectable I/Os. Table 2-8 on page 2-11 contains the I/O standards supported by the Axcelerator family, and Table 2-10 on page 2-11 compares the features of the different I/O standards. Each I/O provides programmable slew rates, drive strengths, and weak pull-up and weak pull-down circuits. I/O standards, except 3.3V PCI and 3.3V PCI-X, are capable of hot insertion. 3.3V PCI and 3.3V PCI-X are 5V tolerant with the aid of an external resistor. The input buffer has an optional user-configurable delay element. The element can reduce or eliminate the hold time requirement for input signals registered within the I/O cell. The value for the delay is set on a bank-wide basis. Note that the delay WILL be a function of process variations as well as temperature and voltage changes. Each I/O includes three registers: an input (InReg), an output (OutReg), and an enable register (EnReg). I/Os are organized into banks, and there are eight banks per device -- two per side (Figure 2-6 on page 2-15). Each I/O bank has a common VCCI, the supply voltage for its I/Os. For voltage-referenced I/Os, each bank also has a common reference-voltage bus, VREF. While VREF must have a common voltage for an entire I/O bank, its location is user-selectable. In other words, any user I/O in the bank can be selected to be a VREF. The location of the VREF pin should be selected according to the following rules: * Any pin that is assigned as a VREF can control a maximum of eight user I/O pad locations in each direction (16 total maximum) within the same I/O bank. * I/O pad locations listed as no connects are counted as part of the 16 maximum. In many cases, this leads to fewer than eight user I/O package pins in each direction being controlled by a VREF pin. * Dedicated I/O pins (GND, VCCI...) are counted as part of the 16. * The two user I/O pads immediately adjacent on each side of the VREF pin (four in total) may only be used as an input. The exception is when there is a VCCI/ GND pair separating the VREF pin and the user I/O pad location.
The Probe pins are used to output data from any userdefined design node within the device (controlled with Silicon Explorer II). These independent diagnostic pins can be used to allow real-time diagnostic output of any signal path within the device. The pins' probe capabilities can be permanently disabled to protect programmed design confidentiality. The probe pins are of LVTTL output levels.
TCK Test Clock
Test clock input for JTAG boundary-scan testing and diagnostic probe (Silicon Explorer II).
TDI Test Data Input
Serial input for JTAG boundary-scan testing and diagnostic probe. TDI is equipped with an internal 10 k pull-up resistor.
TDO Test Data Output
Serial output for JTAG boundary-scan testing.
TMS Test Mode Select
The TMS pin controls the use of the IEEE 1149.1 boundary-scan pins (TCK, TDI, TDO, TRST). TMS is equipped with an internal 10 k pull-up resistor.
TRST Boundary Scan Reset Pin
The TRST pin functions as an active-low input to asynchronously initialize or reset the boundary scan circuit. The TRST pin is equipped with a 10 k pull-up resistor.
Special Functions
LP Low Power Pin
The LP pin controls the low power mode of Axcelerator devices. The device is placed in the low power mode by connecting the LP pin to logic high. To exit the low power mode, the LP pin must be set Low. Additionally, the LP pin must be set Low during chip powering-up or chip powering-down operations. See "Low Power Mode" on page 2-89 for more details.
NC No Connection
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device.
2. Do not use an external resister to pull the I/O above VCCI for a higher logic "1" voltage level. The desired higher logic "1" voltage level will be degraded due to a small I/O current, which exists when the I/O is pulled up above VCCI.
2 -1 0
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Axcelerator Family FPGAs
The differential amplifier supply voltage VCCDA should be connected to 3.3V. A user can gain access to the various I/O standards in three ways: * Instantiate specific library macros that represent the desired specific standard
Use generic I/O macros and then use Actel Designer's PinEditor to specify the desired I/O standards (please note that this is not applicable to differential standards) * A combination of the first two methods. Please refer to the I/O Features in Axcelerator Family Devices application note and the Antifuse Macro Library Guide for more details.
Input Reference Voltage (VREF) N/A N/A N/A N/A N/A 1.0 1.0 0.75 1.5 1.25 N/A N/A Board Termination Voltage (VTT) N/A N/A N/A N/A N/A 1.2 1.2 0.75 1.5 1.25 N/A N/A
*
Table 2-8 * I/O Standards Supported by the Axcelerator Family I/O Standard LVTTL LVCMOS 2.5V LVCMOS 1.8V LVCMOS 1.5V (JDEC8-11) 3.3V PCI/PCI-X GTL+ 3.3V GTL+ 2.5V* HSTL Class 1 SSTL3 Class 1 and II SSTL2 Class1 and II LVDS LVPECL Input/Output Supply Voltage (VCCI) 3.3 2.5 1.8 1.5 3.3 3.3 2.5 1.5 3.3 2.5 2.5 3.3
Note: *2.5V GTL+ is not supported across the full military temperature range. Table 2-9 * Supply Voltages VCCA 1.5V 1.5V 1.5V 1.5V VCCI 1.5V 1.8V 2.5V 3.3V Input Tolerance 3.3V 3.3V 3.3V 3.3V Output Drive Level 1.5V 1.8V 2.5V 3.3V
Table 2-10 * I/O Features Comparison I/O Assignment LVTTL 3.3V PCI, 3.3V PCI-X LVCMOS2.5V LVCMOS1.8V LVCMOS1.5V (JESD8-11) Voltage-Referenced Input Buffer Differential, LVDS/LVPECL, Input Differential, LVDS/LVPECL, Output Notes: 1. 2. 3. 4. Can be implemented with an IDT bus switch. Can be implemented with an external resistor. The OE input of the output buffer must be deasserted permanently (handled by software). The OE input of the output buffer must be asserted permanently (handled by software). Clamp Diode No Yes No No No No No No Hot Insertion Yes No Yes Yes Yes Yes Yes Yes 5V Tolerance Yes
1
Input Buffer
Output Buffer
Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled/Disabled Enabled Disabled Disabled3 Enabled4
Yes1, 2 No No No No No No
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Axcelerator Family FPGAs
5V Tolerance
There are two schemes to achieve 5V tolerance: 1. 3.3V PCI and 3.3V PCI-X are the only I/O standards that directly allow 5V tolerance. To implement this, an internal clamp diode between the input pad and the VCCI pad is enabled so that the voltage at the input pin is clamped as shown in EQ 2-3: Vinput = VCCI + Vdiode = 3.3V + 0.8V = 4.1V
EQ 2-3
recommends that users not exceed eight simultaneous switching outputs (SSO) per each VCCI/GND pair. To ease this potential burden on designers, Actel has designed all of the Axcelerator BGAs3 to not exceed this limit with the exception of the CS180, which has an I/O to VCCI/GND pair ratio of nine to one. Please refer to the Simultaneous Switching Noise and Signal Integrity application note for more information.
An external series resister (~100) is required between the input pin and the 5V signal source to limit the current (Figure 2-3).
I/O Banks and Compatibility
Since each I/O bank has its own user-assigned input reference voltage (VREF) and an input/output supply voltage (VCCI), only I/Os with compatible standards can be assigned to the same bank. Table 2-11 shows the compatible I/O standards for a common VREF (for voltage-referenced standards). Similarly, Table 2-12 shows compatible standards for a common VCCI.
Table 2-11 * Compatible I/O Standards for Different VREF Values
Non-Actel Part
5V
Actel FPGA
3.3V PCI clamp diode 3.3V
Rext
VREF 1.5V 1.25V
Compatible Standards SSTL 3 (Class I and II) SSTL 2 (Class I and II) GTL+ (2.5V and 3.3V Outputs) HSTL (Class I)
Figure 2-3 * Use of an External Resistor for 5V Tolerance
1.0V 0.75V
2. 5V tolerance can also be achieved with 3.3V I/O standards (3.3V PCI, 3.3V PCI-X, and LVTTL) using a bus-switch product (e.g. IDTQS32X2384). This will convert the 5V signal to a 3.3V signal with minimum delay (Figure 2-4).
5V 5V 3.3V 20X 3.3V
Table 2-12 * Compatible I/O Standards for Different VCCI Values VCCI1 3.3V 3.3V 2.5V 2.5V 1.8V 1.5V Notes: 1. VCCI is used for both inputs and outputs 2. VCCI tolerance is 5% Compatible Standards LVTTL, PCI, PCI-X, LVPECL, GTL+ 3.3V SSTL 3 (Class I and II), LVTTL, PCI, LVPECL LVCMOS 2.5V, GTL+ 2.5V, LVDS LVCMOS 1.8V LVCMOS 1.5V, HSTL Class I
2
VREF 1.0 1.5 1.0 1.25 N/A 0.75
LVCMOS 2.5V, SSTL 2 (Classes I and II), LVDS2
Figure 2-4 * Bus Switch IDTQS32X2384
Simultaneous Switching Outputs (SSO)
When multiple output drivers switch simultaneously, they induce a voltage drop in the chip/package power distribution. This simultaneous switching momentarily raises the ground voltage within the device relative to the system ground. This apparent shift in the ground potential to a non-zero value is known as simultaneous switching noise (SSN) or more commonly, ground bounce. SSN becomes more of an issue in high pin count packages and when using high performance devices such as the Axcelerator family. Based upon testing, Actel
Table 2-13 on page 2-13 summarizes the different combinations of voltages and I/O standards that can be used together in the same I/O bank. Note that two I/O standards are compatible if: * * Their VCCI values are identical. Their VREF standards are identical (if applicable).
3. The user should note that in Bank 8 of both AX1000-FG484 and AX500-FG484, there are local violations of this 8:1 ratio.
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For example, if LVTTL 3.3V (VREF= 1.0V) is used, then the other available (i.e. compatible) I/O standards in the same bank are LVTTL 3.3V PCI/PCI-X, GTL+, and LVPECL.
Table 2-13 * Legal I/O Usage Matrix
Also note that when multiple I/O standards are used within a bank, the voltage tolerance will be limited to the minimum tolerance of all I/O standards used in the bank.
LVCMOS1.5V (JESD8-11)
SSTL2 Class I & II (2.5V)
SSTL3 Class I & II (3.3V)
HSTL Class I (1.5V)
3.3V PCI/PCI-X
I/O Standard LVTTL 3.3V (VREF=1.0V) LVTTL 3.3V(VREF=1.5V) LVCMOS 2.5V (VREF=1.0V) LVCMOS 2.5V (VREF=1.25V) LVCMOS1.8V LVCMOS1.5V (VREF=1.75V) (JESD8-11) 3.3V PCI/PCI-X (VREF=1.0V) 3.3V PCI/PCI-X (VREF=1.5V) GTL + (3.3V) GTL + (2.5V) HSTL Class I SSTL2 Class I & II SSTL3 Class I & II LVDS (VREF=1.0V) LVDS (VREF=1.25V) LVPECL (VREF=1.0V) LVPECL (VREF=1.5V) Notes:
- - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - -
- - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - - - -
- - - - - - - - - - - - - - -
- - - - - - - - - - - - - -
- - - - - - - - - - - - -
- - - - - - - - - - - -
1. Note that GTL+ 2.5V is not supported across the full military temperature range. 2. A "" indicates whether standards can be used within a bank at the same time. Examples: a) LVTTL can be used with 3.3V PCI and GTL+ (3.3V), when VREF = 1.0V (GTL+ requirement). b) LVTTL can be used with 3.3V PCI and SSTL3 Class I and II, when VREF = 1.5V (SSTL3 requirement).
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LVPECL (3.3V) - - - - - - - - -
2-13
LVCMOS 2.5V
LVCMOS1.8V
GTL + (3.3V)
GTL + (2.5V)
LVDS (2.5V)
LVTTL 3.3V
Axcelerator Family FPGAs
I/O CLUSTER
routed input track
EnReg DIN YOUT
P PAD
OEP
routed input track
BSR
routed input track
OutREg DIN YOUT
routed input track
UOP
I/O slew rate drive strength programmable delay VREF
output track
Y
InReg DCIN
output track
UIP
FPGA LOGIC CORE
N PAD
routed input track
EnReg DIN YOUT
routed input track
OEN
routed input track
BSR
routed input track
OutREg DIN YOUT
UON
I/O slew rate drive strength programmable delay VREF
output track
Y
InReg DCIN
output track
UIN
Figure 2-5 * I/O Cluster Interface
I/O Clusters
Each I/O cluster incorporates two I/O modules, four RX modules and two TX modules, and a buffer module. In turn, each I/O module contains one Input Register (InReg), one Output Register (OutReg), and one Enable Register (EnReg) (Figure 2-5).
fuse option in the Designer software, when checked, causes all I/O registers to output logic High at device power-up.
Using the Weak Pull-Up and Pull-Down Circuits
Each Axcelerator I/O comes with a weak pull-up/down circuit (on the order of 10 k). I/O macros are provided for combinations of pull up/down for LVTTL, LVCMOS (2.5V, 1.8V, and 1.5V) standards. These macros can be instantiated if a keeper circuit for any input buffer is required.
Using an I/O Register
To access the I/O registers, registers must be instantiated in the netlist and then connected to the I/Os. Usage of each I/O register (register combining) is individually controlled and can be selected/deselected using the PinEditor tool in Actel's Designer software. I/O register combining can also be controlled at the device level, affecting all I/Os. Please note, the I/O register option is deselected by default in any given design.4 In addition, Designer software provides a global option to enable/disable the usage of registers in the I/Os. This option is design-specific. The setting for each individual I/O overrides this global option. Furthermore, the global set
Customizing the I/O
* A five-bit programmable input delay element is associated with each I/O. The value of this delay is set on a bank-wide basis (Table 2-14 on page 2-15). It is optional for each input buffer within the bank (i.e. the user can enable or disable the delay element for the I/O). When the input buffer drives a register within the I/O, the delay element is
4. Please note that register combining for multi fanout nets is not supported.
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activated by default to ensure a zero hold-time. The default setting for this property can be set in Designer. When the input buffer does not drive a register, the delay element is deactivated to provide higher performance. Again, this can be overridden by changing the default setting for this property in Designer. * The slew-rate value for the LVTTL output buffer can be programmed and can be set to either slow or fast. The drive strength value for LVTTL output buffers can be programmed as well. There are four different drive strength values - 8mA, 12mA, 16mA, or 24mA - that can be specified in Designer.5
Using the Voltage-Referenced I/O Standards
Using these I/O standards is similar to that of singleended I/O standards. Their settings can be changed in Designer.
Using DDR (Double Data Rate)
In Double Data Rate mode, new data is present on every transition of the clock signal. Clock and data lines have identical bandwidth and signal integrity requirements, making it very efficient for implementing very highspeed systems. To implement a DDR, users need to: 1. Instantiate an input buffer (with the required I/O standard) 2. Instantiate the DDR_REG macro (Figure 2-6) 3. Connect the output from the Input buffer to the input of the DDR macro
*
Table 2-14 * Bank-Wide Delay Values Bits Setting 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Delay (ns) 0.54 0.65 0.71 0.83 0.9 1.01 1.08 1.19 1.27 1.39 1.45 1.56 1.64 1.75 1.81 1.93 Bits Setting 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Delay (ns) 2.01 2.13 2.19 2.3 2.38 2.49 2.55 2.67 2.75 2.87 2.93 3.04 3.12 3.23 3.29 3.41
D D
PSET QR QF
CLK CLR
Figure 2-6 * DDR Register
Macros for Specific I/O Standards
There are different macro types for any I/O standard or feature that determine the required VCCI and VREF voltages for an I/O. The generic buffer macros require the LVTTL standard with slow slew rate and 24mA-drive strength. LVTTL can support high slew rate but this should only be used for critical signals. Most of the macro symbols represent variations of the six generic symbol types: * * * * * * * CLKBUF: Clock Buffer HCLKBUF: Hardwired Clock Buffer INBUF: Input Buffer OUTBUF: Output Buffer TRIBUF: Tristate Buffer BIBUF: Bidirectional Buffer Differential I/O standard macros: The LVDS and LVPECL macros either have a pair of differential
Note: Delay values are approximate and will vary with process, temperature, and voltage.
Using the Differential I/O Standards
Differential I/O macros should be instantiated in the netlist. The settings for these I/O standards cannot be changed inside Designer. Please note that there are no tristated or bidirectional I/O buffers for differential standards.
Other macros include the following:
5. These values are minimum drive strengths.
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Axcelerator Family FPGAs
inputs (e.g. INBUF_LVDS) or a pair of differential outputs (e.g. OUTBUF_LVPECL). * Pull-up and pull-down variations of the INBUF, BIBUF, and TRIBUF macros. These are available only with TTL and LVCMOS thresholds. They can be used to model the behavior of the pull-up and pull-down resistors available in the architecture. Whenever an input pin is left unconnected, the output pin will either go high or low rather than unknown. This allows users to leave inputs *
unconnected without having the negative effect on simulation of propagating unknowns. DDR_REG macro. It can be connected to any I/O standard input buffers (i.e. INBUF) to implement a double data rate register. Designer software will map it to the I/O module in the same way it maps the other registers to the I/O module.
Table 2-15, Table 2-16 on page 2-17, and Table 2-17 on page 2-17 list all the available macro names differentiated by I/O standard, type, slew rate, and drive strength.
Table 2-15 * Macros for Single-Ended I/O Standards Standard LVTTL VCCI 3.3V Macro Names CLKBUF, HCLKBUF INBUF, OUTBUF, OUTBUF_S_8, OUTBUF_S_12, OUTBUF_S_16, OUTBUF_S_24, OUTBUF_H_8, OUTBUF_H_12, OUTBUF_H_16, OUTBUF_H_24, TRIBUF, TRIBUF_S_8, TRIBUF_S_12, TRIBUF_S_16, TRIBUF_S_24, TRIBUF_H_8, TRIBUF_H_12, TRIBUF_H_16, TRIBUF_H_24, BIBUF, BIBUF_S_8, BIBUF_S_12, BIBUF_S_16, BIBUF_S_24, BIBUF_H_8, BIBUF_H_12, BIBUF_H_16, BIBUF_H_24, CLKBUF_PCI, HCLKBUF_PCI, INBUF_PCI, OUTBUF_PCI, TRIBUF_PCI, BIBUF_PCI CLKBUF_PCI-X, HCLKBUF_PCI-X, INBUF_PCI-X, OUTBUF_PCI-X, TRIBUF_PCI-X, BIBUF_PCI-X CLKBUF_LVCMOS25, HCLKBUF_LVCMOS25, INBUF_LVCMOS25, OUTBUF_LVCMOS25, TRIBUF_LVCMOS25, BIBUF_LVCMOS25 CLKBUF_LVCMOS18, HCLKBUF_LVCMOS18, INBUF_LVCMOS18, OUTBUF_LVCMOS18, TRIBUF_LVCMOS18, BIBUF_LVCMOS18 CLKBUF_LVCMOS15, HCLKBUF_LVCMOS15, INBUF_LVCMOS15, OUTBUF_LVCMOS15, TRIBUF_LVCMOS15, BIBUF_LVCMOS15
3.3V PCI
3.3V
3.3V PCI-X
3.3V
LVCMOS25
2.5V
LVCMOS18
1.8V
LVCMOS15 (JESD8-11)
1.5V
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Table 2-16 * I/O Macros for Differential I/O Standards Standard LVPECL LVDS VCCI 3.3V 2.5V Macro Names CLKBUF_LVPECL, HCLKBUF_LVPECL, INBUF_LVPECL, OUTBUF_LVPECL, CLKBUF_LVDS, HCLKBUF_LVDS, INBUF_LVDS, OUTBUF_LVDS,
Table 2-17 * I/O Macros for Voltage-Referenced I/O Standards Standard GTL+ GTL+ SSTL2 Class I SSTL2 Class II SSTL3 Class I SSTL3 Class II HSTL Class I VCCI 3.3V 2.5V 2.5V 2.5V 3.3V 3.3V 1.5V VREF 1.0V 1.0V 1.25V 1.25V 1.5V 1.5V 0.75V Macro Names CLKBUF_GTP33, HCLKBUF_GTP33, INBUF_GTP33, OUTBUF_GTP33, TRIBUF_GTP33, BIBUF_GTP33 CLKBUF_GTP25, HCLKBUF_GTP25, INBUF_GTP25, OUTBUF_GTP25, TRIBUF_GTP25, BIBUF_GTP25 CLKBUF_SSTL2_I, HCLKBUF_SSTL2_I, TRIBUF_SSTL2_I, BIBUF_SSTL2_I CLKBUF_SSTL2_II, HCLKBUF_SSTL2_II, TRIBUF_SSTL2_II, BIBUF_SSTL2_II CLKBUF_SSTL3_I, HCLKBUF_SSTL3_I, TRIBUF_SSTL3_I, BIBUF_SSTL3_I CLKBUF_SSTL3_II, HCLKBUF_SSTL3_II, TRIBUF_SSTL3_II, BIBUF_SSTL3_II INBUF_SSTL2_I, INBUF_SSTL2_II, INBUF_SSTL3_I, INBUF_SSTL3_II, OUTBUF_SSTL2_I, OUTBUF_SSTL2_II, OUTBUF_SSTL3_I, OUTBUF_SSTL3_II,
CLKBUF_HSTL_I, HCLKBUF_HSTL_I, INBUF_HSTL_I, OUTBUF_HSTL_I, TRIBUF_HSTL_I, BIBUF_HSTL_I
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Axcelerator Family FPGAs
User I/O Naming Conventions
Due to the complex and flexible nature of the Axcelerator family's user I/Os, a naming scheme is used to show the details of the I/O. The naming scheme explains to which bank an I/O belongs, as well as the pairing and pin polarity for differential I/Os (Figure 2-7).
VCCA GND V COMPLD V CCPLD V COMPLC V CCPLC VCCDA GND V COMPLB V CCPLB V COMPLA V CCPLA
V PUMP
GND V CCDA
PRB PRA V CCI 0 GND
GND
V CCI 1
GND VCCDA
I/O BANK 2
VCCI 7 GND VCCA
GND
VCCDA GND VCCI 6 GND VCCA GND I/O BANK 6
I/O BANK 3
GND V CCDA
Figure 2-7 * I/O Bank and Dedicated Pin Layout
P - Positive Pin/ N- Negative Pin Bank I/D 0 through 7, clockwise from IOB NW Fx refers to an unimplemented feature and can be ignored.
Figure 2-8 * General Naming Schemes
TDO TDI TCK TMS TRST LP Corner1 Corner4 I/O BANK 7 VCCDA GND
Pair number in the bank, starting at 00, clockwise from IOB NW
VCCA GND V CCA GND
I/O BANK 0
I/O BANK 1
Corner2
GND VCCDA
VCCI 2 GND VCCA GND GND VCCDA VCCI 3 GND VCCA GND
AX125
I/O BANK 5
I/O BANK 4
Corner3
GND VCCDA
V CCI 4 GND
V CCA GND V COMPLE V CCPLE V COMPLF V CCPLF PRC PRD V COMPLG V CCPLG V COMPLH V CCPLH GND V CCDA
Examples:
V CCI 5 GND
GND V CCDA
IOxxXBxFx
IO12PB1F1 is the positive pin of the thirteenth pair of the first I/O bank (IOB NE). IO12PB1 combined with IO12NB1 form a differential pair. For those I/Os that can be employed either as a user I/O or as a special function, the following nomenclature is used: IOxxXBxFx/special_function_name IOxxPB1Fx/xCLKx this pin can be configured as a clock input or as a user I/O.
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I/O Standard Electrical Specifications
Table 2-18 * Input Capacitance Symbol CIN CINCLK Parameter Input Capacitance Input Capacitance on Clock Pin Conditions VIN=0, f=1.0 MHz VIN=0, f=1.0 MHz Min. Max. 10 10 Units pF pF
PAD
IN
INBUF
Y
Input High ln Vtrip VCCA Y GND
Figure 2-9 * Input Buffer Delays
Vtrip
0V
50% t DP (Rising) t DP (Falling)
50%
ln
TRIBUF
OUT Pad
To AC test loads (shown below)
En VCCA 50% ln VOH Out VOL Vtrip tPY
(tDLH)
VCCA 50% GND En VCCI/VTT Vtrip tPY
(tDHL)
VCCA 50% GND VTT 10% VOL Out GND/VTT
tENHZ
50%
50% En
50% GND
Out
Vtrip
VOH Vtrip
tENHZ
90% VTT
tENLZ
tENLZ
Figure 2-10 * Output Buffer Delays
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Axcelerator Family FPGAs
I/O Module Timing Characteristics
Out D Q
OutReg
OE D EnReg Q IN D D Q InReg Q
CLK CLK (Routed or Hardwired)
Figure 2-11 * Timing Model
D
tSUD CLK
tHD
tICLKQ Q tHASYN CLR tWASYN tREASYN tCLR
tCPWHL
tCPWLH
tPRESET PRESET tSUE E tHE tWASYN
tHASYN
tREASYN
Figure 2-12 * Input Register Timing Characteristics
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Axcelerator Family FPGAs
D
tSUD CLK
tHD
tOCLKQ Q tHASYN CLR tWASYN tREASYN tCLR
tCPWHL
tCPWLH
tPRESET PRESET tSUE E tHE tWASYN
tHASYN
tREASYN
Figure 2-13 * Output Register Timing Characteristics
D
tSUD CLK
tHD
tOCLKQ Q tHASYN CLR tWASYN tREASYN tCLR
tCPWHL
tCPWLH
tPRESET PRESET tSUE E tHE tWASYN
tHASYN
tREASYN
Figure 2-14 * Output Enable Register Timing Characteristics
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Axcelerator Family FPGAs
3.3V LVTTL
Low-Voltage Transistor-Transistor Logic is a general purpose standard (EIA/JESD) for 3.3V applications. It uses an LVTTL input buffer and push-pull output buffer.
Table 2-19 * DC Input and Output Levels VIL Min,V -0.3 Max,V 0.8 Min,V 2.0 VIH Max,V 3.6 VOL Max,V 0.4 VOH Min,V 2.4 IOL mA 24 IOH mA -24
AC Loadings
R=1k Test Point for tpd Test Point for tristate R to VCCI for tplz/tpzl R to GND for tphz/tpzh 35 pF for tpzh/tpzl 5 pF for tphz/tplz
35 pF
Figure 2-15 * AC Test Loads Table 2-20 * AC Waveforms, Measuring Points, and Capacitive Load Input Low (V) 0 * Measuring Point = Vtrip Input High (V) 3.0 Measuring Point* (V) 1.40 VREF (typ) (V) N/A Cload (pF) 35
Timing Characteristics
Table 2-21 * 3.3V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
LVTTL Output Drive Strength = 1 (8mA) / Low Slew Rate tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 1.72 14.32 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 1.96 16.31 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.31 19.19 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Table 2-21 * 3.3V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C (Continued) '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
LVTTL Output Drive Strength = 2 (12mA) / Low Slew Rate tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 1.72 12.18 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 1.96 13.87 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.31 16.31 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
LVTTL Output Drive Strength =3 (16mA) / Low Slew Rate Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 1.72 11.07 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 1.96 12.61 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.31 14.83 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Axcelerator Family FPGAs
Table 2-21 * 3.3V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C (Continued) '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
LVTTL Output Drive Strength = 4 (24mA) / Low Slew Rate tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 1.72 10.49 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 1.96 11.95 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.31 14.05 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
LVTTL Output Drive Strength = 1 (8mA) / High Slew Rate Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 1.72 4.26 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 1.96 4.86 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.31 5.72 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2 -2 4
v2.7
Axcelerator Family FPGAs
Table 2-21 * 3.3V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C (Continued) '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
LVTTL Output Drive Strength = 2 (12mA) / High Slew Rate tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 1.72 3.34 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 1.96 3.80 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.31 4.47 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
LVTTL Output Drive Strength =3 (16mA) / High Slew Rate Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 1.72 3.16 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 1.96 3.60 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.31 4.24 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
v2.7
2-25
Axcelerator Family FPGAs
Table 2-21 * 3.3V LVTTL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C (Continued) '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
LVTTL Output Drive Strength = 4 (24mA) / High Slew Rate tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 1.72 3.03 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 1.96 3.45 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.31 4.06 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2 -2 6
v2.7
Axcelerator Family FPGAs
2.5V LVCMOS
Low-Voltage Complementary Metal-Oxide Semiconductor for 2.5V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 2.5V applications. It uses a 3.3V tolerant CMOS input buffer and a push-pull output buffer.
Table 2-22 * DC Input and Output Levels VIL Min,V -0.3 Max,V 0.7 Min,V 1.7 VIH Max,V 3.6 VOL Max,V 0.4 VOH Min,V 2.0 IOL mA 12 IOH mA -12
AC Loadings
R=1k Test Point for tpd Test Point for tristate R to VCCI for tplz/tpzl R to GND for tphz/tpzh 35 pF for tpzh/tpzl 5 pF for tphz/tplz
35 pF
Figure 2-16 * AC Test Loads Table 2-23 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 * Measuring Point = Vtrip Input High (V) 2.5 Measuring Point* (V) 1.25 VREF (typ) (V) N/A Cload (pF) 35
Timing Characteristics
Table 2-24 * 2.5V LVCMOS I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 2.3V, TJ = 70C '-2' Speed Parameter tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 Description Min. Max. 1.99 3.24 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 LVCMOS25 I/O Module Timing 2.26 3.69 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.66 4.34 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
v2.7
2-27
Axcelerator Family FPGAs
1.8V LVCMOS
Low-Voltage Complementary Metal-Oxide Semiconductor for 1.8V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.8V applications. It uses a 3.3V tolerant CMOS input buffer and a push-pull output buffer.
Table 2-25 * DC Input and Output Levels VIL Min,V -0.3 Max,V 0.2VCCI Min,V 0.7VCCI VIH Max,V 3.6 VOL Max,V 0.2 VOH Min,V VCCI-0.2 IOL mA 8mA IOH mA -8mA
AC Loadings
R=1k Test Point for tpd Test Point for tristate R to VCCI for tplz/tpzl R to GND for tphz/tpzh 35 pF for tpzh/tpzl 5 pF for tphz/tplz
35 pF
Figure 2-17 * AC Test Loads Table 2-26 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 * Measuring Point = Vtrip Input High (V) 1.8 Measuring Point* (V) 0.5VCCI VREF (typ) (V) N/A Cload (pF) 35
Timing Characteristics
Table 2-27 * 1.8V LVCMOS I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 1.7V, TJ = 70C '-2' Speed Parameter tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 Description Min. Max. 3.30 4.54 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 LVCMOS18 Output Module Timing 3.76 5.17 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 4.42 6.08 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
2 -2 8
v2.7
Axcelerator Family FPGAs
1.5V LVCMOS (JESD8-11)
Low-Voltage Complementary Metal-Oxide Semiconductor for 1.5V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.5V applications. It uses a 3.3V tolerant CMOS input buffer and a push-pull output buffer.
Table 2-28 * DC Input and Output Levels VIL Min,V -0.5 Max,V 0.35VCCI Min,V 0.65VCCI VIH Max,V 3.6 VOL Max,V 0.4 VOH Min,V VCCI-0.4 IOL mA 8mA IOH mA -8mA
AC Loadings
R=1k Test Point for tpd Test Point for tristate R to VCCI for tplz/tpzl R to GND for tphz/tpzh 35 pF for tpzh/tpzl 5 pF for tphz/tplz
35 pF
Table 2-29 * AC Test Loads Table 2-30 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 * Measuring Point = Vtrip Input High (V) 1.5 Measuring Point* (V) 0.5VCCI VREF (typ) (V) N/A Cload (pF) 35
Timing Characteristics
Table 2-31 * 1.5V LVCMOS I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 1.4V, TJ = 70C '-2' Speed Parameter tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 Description Min. Max. 3.63 6.02 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 LVCMOS15 (JESD8-11) I/O Module Timing 4.14 6.86 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 4.87 8.07 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
v2.7
2-29
Axcelerator Family FPGAs
3.3V PCI, 3.3V PCI-X
Peripheral Component Interface for 3.3V standard specifies support for both 33 MHz and 66 MHz PCI bus applications. It uses an LVTTL input buffer and a push-pull output buffer. The input and output buffers are 5V tolerant with the aid of external components. Axcelerator 3.3V PCI and 3.3V PCI-X buffers are compliant with the PCI Local Bus Specification Rev. 2.1. The PCI Compliance Specification requires the clamp diodes to be able to withstand for 11 ns, -3.5V in undershoot, and 7.1V in overshoot.
Table 2-32 * DC Input and Output Levels VIL Min,V PCI PCI-X -0.5 -0.5 Max,V 0.3VCCI 0.35VCCI Min,V 0.5VCCI 0.5VCCI VIH Max,V VCCI+0.5 VCCI+0.5 VOL Max,V VOH Min,V IOL mA IOH mA
(per PCI specification) (per PCI specification)
AC Loadings
R=1k Test Point for tristate
R to VCCI for tplz/tpzl R to GND for tphz/tpzh 35 pF for tpzl/tpzh 5 pF for tphz/tplz
R=25 Test point for data
R to V CCI for tpl R to GND for tph 10pF
GND
Figure 2-18 * AC Test Loads Table 2-33 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) * Measuring Point = Vtrip Input High (V) Measuring Point* (V) VREF (typ) (V) N/A Cload (pF) 10 (Per PCI Spec and PCI-X Spec)
2 -3 0
v2.7
Axcelerator Family FPGAs
Timing Characteristics
Table 2-34 * 3.3V PCI I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter 3.3V PCI Output Module Timing tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 1.61 1.95 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 0.00 0.31 0.31 ns 1.83 2.22 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 2.16 2.62 2.87 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
Table 2-35 * 3.3V PCI-X I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 Description Min. Max. 1.61 2.14 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 3.3V PCI-X Output Module Timing 1.83 2.44 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 ns 2.16 2.87 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
v2.7
2-31
Axcelerator Family FPGAs
Voltage-Referenced I/O Standards
GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It requires a differential amplifier input buffer and an Open Drain output buffer. The VCCI pin should be connected to 2.5V or 3.3V. Note that 2.5V GTL+ is not supported across the full military temperature range.
Table 2-36 * DC Input and Output Levels VIL Min,V N/A Max,V VREF-0.1 Min,V VREF+0.1 VIH Max,V N/A VOL Max,V 0.6 VOH Min,V NA IOL mA NA IOH mA NA
AC Loadings
VTT 25 Test Point 10 pF
Figure 2-19 * AC Test Loads Table 2-37 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF-0.2 * Measuring Point = Vtrip Input High (V) VREF+0.2 Measuring Point* (V) VREF VREF (typ) (V) 1.0 Cload (pF) 10
Timing Characteristics
Table 2-38 * 2.5V GTL+ I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 2.3V, TJ = 70C '-2' Speed Parameter 2.5V GTL+ I/O Module Timing tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 1.75 1.01 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 1.99 1.15 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.35 1.36 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
2 -3 2
v2.7
Axcelerator Family FPGAs
Table 2-39 * 3.3V GTL+ I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter 3.3V GTL+I/O Module Timing tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 1.75 1.01 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 1.99 1.15 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.35 1.36 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
v2.7
2-33
Axcelerator Family FPGAs
HSTL Class I
High-Speed Transceiver Logic is a general-purpose high-speed 1.5V bus standard (EIA/JESD8-6). The Axcelerator devices support Class I. This requires a differential amplifier input buffer and a push-pull output buffer.
Table 2-40 * DC Input and Output Levels VIL Min,V -0.3 Max,V VREF-0.1 Min,V VREF+0.1 VIH Max,V 3.6 VOL Max,V 0.4 VOH Min,V VCC-0.4 IOL mA 8 IOH mA -8
AC Loadings
VTT 50 Test Point 20 pF
Figure 2-20 * AC Test Loads Table 2-41 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF-0.5 * Measuring Point = Vtrip Input High (V) VREF+0.5 Measuring Point* (V) VREF VREF (typ) (V) 0.75 Cload (pF) 20
Timing Characteristics
Table 2-42 * 1.5V HSTL Class I I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 1.425V, TJ = 70C '-2' Speed Parameter tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 Description Min. Max. 1.84 4.93 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 1.5V HSTL Class I I/O Module Timing 2.10 5.62 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.47 6.61 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
2 -3 4
v2.7
Axcelerator Family FPGAs
SSTL2
Stub Series Terminated Logic for 2.5V is a general-purpose 2.5V memory bus standard (JESD8-9). The Axcelerator devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output buffer.
Class I
Table 2-43 * DC Input and Output Levels VIL Min,V -0.3 Max,V VREF-0.2 Min,V VREF+0.2 VIH Max,V 3.6 VOL Max,V VREF-0.57 VOH Min,V VREF+0.57 IOL mA 7.6 IOH mA -7.6
AC Loadings
VTT 50 Test Point 25 30 pF
Figure 2-21 * AC Test Loads Table 2-44 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF-0.75 * Measuring Point = Vtrip Input High (V) VREF+0.75 Measuring Point* (V) VREF VREF (typ) (V) 1.25 Cload (pF) 30
Timing Characteristics
Table 2-45 * 2.5V SSTL2 Class I I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 2.3V, TJ = 70C '-2' Speed Parameter tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 Description Min. Max. 1.86 2.43 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 2.5V SSTL2 Class I I/O Module Timing 2.12 2.76 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.50 3.25 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
v2.7
2-35
Axcelerator Family FPGAs
Class II
Table 2-46 * DC Input and Output Levels VIL Min,V -0.3 Max,V VREF-0.2 Min,V VREF+0.2 VIH Max,V 3.6 VOL Max,V VREF-0.8 VOH Min,V VREF+0.8 IOL mA 15.2 IOH mA -15.2
AC Loadings
VTT 25 Test Point 25 30 pF
Figure 2-22 * AC Test Loads Table 2-47 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF-0.75 * Measuring Point = Vtrip Input High (V) VREF+0.75 Measuring Point* (V) VREF VREF (typ) (V) 1.25 Cload (pF) 30
Timing Characteristics
Table 2-48 * 2.5V SSTL2 Class II I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 2.3V, TJ = 70C '-2' Speed Parameter tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 Description Min. Max. 1.93 2.43 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 2.5V SSTL2 Class II I/O Module Timing 2.20 2.76 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.59 3.25 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
2 -3 6
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Axcelerator Family FPGAs
SSTL3
Stub Series Terminated Logic for 3.3V is a general-purpose 3.3V memory bus standard (JESD8-8). The Axcelerator devices support both classes of this standard. This requires a differential amplifier input buffer and a push-pull output buffer.
Class I
Table 2-49 * DC Input and Output Levels VIL Min,V -0.3 Max,V VREF-0.2 Min,V VREF+0.2 VIH Max,V 3.6 VOL Max,V VREF-0.6 VOH Min,V VREF+0.6 IOL mA 8 IOH mA -8
AC Loadings
VTT 50 Test Point 25 30 pF
Figure 2-23 * AC Test Loads Table 2-50 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF-1.0 *Measuring Point = Vtrip Input High (V) VREF+1.0 Measuring Point* (V) VREF VREF (typ) (V) 1.50 Cload (pF) 30
Timing Characteristics
Table 2-51 * 3.3V SSTL3 Class I I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 Description Min. Max. 1.82 2.21 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 3.3V SSTL3 Class I I/O Module Timing 2.07 2.52 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.44 2.96 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
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2-37
Axcelerator Family FPGAs
Class II
Table 2-52 * DC Input and Output Levels VIL Min,V -0.3 Max,V VREF-0.2 Min,V VREF+0.2 VIH Max,V 3.6 VOL Max,V VREF-0.8 VOH Min,V VREF+0.8 IOL mA 16 IOH mA -16
AC Loadings
VTT 25 Test Point 25 30 pF
Figure 2-24 * AC Test Loads Table 2-53 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) VREF-1.0 * Measuring Point = Vtrip Input High (V) VREF+1.0 Measuring Point* (V) VREF VREF (typ) (V) 1.50 Cload (pF) 30
Timing Characteristics
Table 2-54 * 3.3V SSTL3 Class II I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 Description Min. Max. 1.88 2.21 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 3.3V SSTL3 Class II I/O Module Timing 2.14 2.52 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.53 2.96 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
2 -3 8
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Axcelerator Family FPGAs
Differential Standards
Physical Implementation
Implementing differential I/O standards requires the configuration of a pair of external I/O pads, resulting in a single internal signal. To facilitate construction of the differential pair, a single I/O Cluster contains the resources for a pair of I/Os. Configuration of the I/O Cluster as a differential pair is handled by Actel's Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with these standards.
LVDS
Low-Voltage Differential Signal (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit is carried through two signal lines, so two pins are needed. It also requires an external resistor termination. The voltage swing between these two signal lines is approximately 350 mV.
OUTBUF_LVDS
FPGA
P
165 140
ZO=50 100 ZO=50
P
FPGA + -
INBUF_LVDS
N
165
N
Figure 2-25 * LVDS Board-Level Implementation
The LVDS circuit consists of a differential driver connected to a terminated receiver through a constantimpedance transmission line. The receiver is a widecommon-mode-range differential amplifier. The common-mode range is from 0.2V to 2.2V for a differential input with 400 mV swing. To implement the driver for the LVDS circuit, drivers from two adjacent I/O cells are used to generate the differential signals (note that the driver is not a currentmode driver). This driver provides a nominal constant
Table 2-55 * DC Input and Output Levels DC Parameter VCCI1 VOH VOL VODIFF VOCM VICM2 Supply Voltage Output High Voltage Output Low Voltage Differential Output Voltage Output Common Mode Voltage Input Common Mode Voltage Description
current of 3.5 mA. When this current flows through a 100 termination resistor on the receiver side, a voltage swing of 350 mV is developed across the resistor. The direction of the current flow is controlled by the data fed to the driver. An external-resistor network (three resistors) is needed to reduce the voltage swing to about 350 mV. Therefore, four external resistors are required, three for the driver and one for the receiver.
Min. 2.375 1.25 0.9 250 1.125 0.2
Typ. 2.5 1.425 1.075 350 1.25 1.25
Max. 2.625 1.6 1.25 450 1.375 2.2
Units V V V mV V V
1. +/- 5% 2. Differential input voltage =+/-350mV.
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Axcelerator Family FPGAs
Table 2-56 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 1.2-0.125 * Measuring Point = Vtrip Input High (V) 1.2+0.125 Measuring Point* (V) 1.2
Timing Characteristics
Table 2-57 * LVDS I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 2.3V, TJ = 70C '-2' Speed Parameter LVDS Output Module Timing tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 1.84 2.36 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 2.10 2.69 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.47 3.16 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
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Axcelerator Family FPGAs
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit is carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The voltage swing between these two signal lines is approximately 850 mV.
FPGA
OUTBUF_LVPECL
P
100 187 100
ZO=50 100
P
FPGA + -
INBUF_LVPECL
N
ZO=50
N
Figure 2-26 * LVPECL Board-Level Implementation
The LVPECL circuit is similar to the LVDS scheme. It requires four external resistors, three for the driver and one for the receiver. The values for the three driver resistors are different from that of LVDS since the output voltage levels are different. Please note that the VOH levels are 200 mV below the standard LVPECL levels.
Table 2-58 * DC Input and Output Levels Min. DC Parameter VCCI VOH VOL VIH VIL Differential Input Voltage 1.8 0.96 1.49 0.86 0.3 Min. 3 2.11 1.27 2.72 2.125 1.92 1.06 1.49 0.86 0.3 Max. Min. 3.3 2.28 1.43 2.72 2.125 2.13 1.3 1.49 0.86 0.3 Typ. Max. Min. 3.6 2.41 1.57 2.72 2.125 Max. Max. Units V V V V V V
Table 2-59 * AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 1.6-0.3 * Measuring Point = Vtrip Input High (V) 1.6+0.3 Measuring Point* (V) 1.6
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Axcelerator Family FPGAs
Timing Characteristics
Table 2-60 * LVPECL I/O Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
LVPECL Output Module Timing tDP tPY tICLKQ tOCLKQ tSUD tSUE tHD tHE tCPWHL tCPWLH tWASYN tREASYN tHASYN tCLR tPRESET Input Buffer Output Buffer Clock-to-Q for the I/O input register Clock-to-Q for the IO output register and the I/O enable register Data Input Set-Up Enable Input Set-Up Data Input Hold Enable Input Hold Clock Pulse Width High to Low Clock Pulse Width Low to High Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Asynchronous Clear-to-Q Asynchronous Preset-to-Q 0.43 0.45 0.43 0.10 0.00 0.23 0.23 1.70 2.28 0.67 0.67 0.23 0.26 0.00 0.00 0.48 0.51 0.48 0.10 0.00 0.27 0.27 1.93 2.60 0.77 0.77 0.27 0.30 0.00 0.00 0.57 0.60 0.57 0.10 0.00 0.31 0.31 2.28 3.06 0.90 0.90 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2 -4 2
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Axcelerator Family FPGAs
Module Specifications
C-Cell
Introduction
The C-cell is one of the two logic module types in the AX architecture. It is the combinatorial logic resource in the Axcelerator device. The AX architecture implements a new combinatorial cell that is an extension of the C-cell implemented in the SX-A family. The main enhancement of the new C-cell is the addition of carry-chain logic. The C-cell can be used in a carry-chain mode to construct arithmetic functions. If carry-chain logic is not required, it can be disabled. The C-cell features the following (Figure 2-27): * Eight-input MUX (data: D0-D3, select: A0, A1, B0, B1). User signals can be routed to any one of these inputs. Any of the C-cell inputs (D0-D3, A0, A1, B0, B1) can be tied to one of the four routed clocks (CLKE/F/G/H). Inverter (DB input) can be used to drive a complement signal of any of the inputs to the Ccell.
D1 D3 B0 B1
*
A carry input and a carry output. The carry input signal of the C-cell is the carry output from the Ccell directly to the north. Carry connect for carry-chain logic with a signal propagation time of less than 0.1 ns. A hardwired connection (direct connect) to the adjacent R-cell (Register Cell) for all C-cells on the east side of a SuperCluster with a signal propagation time of less than 0.1 ns.
* *
This layout of the C-cell (and the C-cell Cluster) enables the implementation of over 4,000 functions of up to five bits. For example, two C-cells can be used together to implement a four-input XOR function in a single cell delay. The carry-chain configuration is handled automatically for the user with Actel's extensive macro library (please see Actel's Antifuse Macro Library Guide for a complete listing of available Axcelerator macros). .
CFN FCI
*
0 1 0 1 0 1 01
0 1
D0 D2
DB
A0
A1
FCO
Y
Figure 2-27 * C-Cell
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Axcelerator Family FPGAs
Timing Model and Waveforms
VCCA 50% A, B, D, FCI VCCA 50% Y, FCO GND Y, FCO 50% tPD, tPDC
Figure 2-28 * C-Cell Timing Model and Waveforms
50% GND 50% tPD, tPDC VCCA GND tPD, tPDC 50%
tPD, tPDC
Timing Characteristics
Table 2-61 * C-Cell Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter C-Cell Propagation Delays tPD tPDC tPDB tCCY tCC Any input to output Y Any input to carry chain output (FCO) Any input through DB when one input is used Input to carry chain (FCI) to Y Input to carry chain (FCI) to carry chain output (FCO) 0.74 0.57 0.95 0.61 0.08 0.84 0.64 1.09 0.69 0.09 0.99 0.76 1.28 0.82 0.11 ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
2 -4 4
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Axcelerator Family FPGAs
Carry-Chain Logic
The Axcelerator dedicated carry-chain logic offers a very compact solution for implementing arithmetic functions without sacrificing performance. To implement the carry-chain logic, two C-cells in a Cluster are connected together so the FCO (i.e. carry out) for the two bits is generated in a carry look-ahead scheme to achieve minimum propagation delay from the FCI (i.e. carry in) into the two-bit Cluster. The two-bit carry logic is shown in Figure 2-29. The FCI of one C-cell pair is driven by the FCO of the C-cell pair immediately above it. Similarly, the FCO of one
CFN CFN 0 1 0 1 0 1 0 1 0 1 D1 D3 B0 B1 FCI
C-cell pair, drives the FCI input of the C-cell pair immediately below it (Figure 1-4 on page 1-3 and Figure 2-30 on page 2-46). The carry-chain logic is selected via the CFN input. When carry logic is not required, this signal is deasserted to save power. Again, this configuration is handled automatically for the user through Actel's macro library. The signal propagation delay between two C-cells in the carry-chain sequence is 0.1 ns.
0 1 0 1 0 1 0 1 DCOUT
D1 D3 B0 B1
A0
D0 D2
DB
A1
0 1
0 1 FCO Y
2-45
Y
DB
A0
Figure 2-29 * Axcelerator's Two-Bit Carry Logic
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D0 D2
A1
Axcelerator Family FPGAs
FCI1
C-cell1
C-cell2 DCOUT
R-cell1 DCIN
FCI3
FCO2
DCOUT
DCIN
FCO4
FCI5
n-2 Clusters
FCI(2n-1)
C-cell (2n-1)
C-cell2n DCOUT
R-celln CDIN
FCO2n
Note: The carry-chain sequence can end on either C-cell. Figure 2-30 * Carry-Chain Sequencing of C-cells
Timing Characteristics
Refer to the Table 2-61 on page 2-44 for more information on carry-chain timing.
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Axcelerator Family FPGAs
R-Cell
Introduction
The R-cell, the sequential logic resource of the Axcelerator devices, is the second logic module type in the AX family architecture. It includes clock inputs for all eight global resources of the Axcelerator architecture as well as global presets and clears (Figure 2-31). The main features of the R-cell include the following: * Direct connection to the adjacent logic module through the hardwired connection DCIN. DCIN is driven by the DCOUT of an adjacent C-cell via the Direct-Connect routing resource, providing a connection with less than 0.1 ns of routing delay. The R-cell can be used as a standalone flip-flop. It can be driven by any C-cell or I/O modules through the regular routing structure (using DIN as a routable data input). This gives the option of using the R-Cell as a 2:1 MUXed flip-flop as well. Provision of data enable-input (S0). Independent active-low asynchronous clear (CLR). Independent active-low asynchronous preset (PSET). If both CLR and PSET are low, CLR has higher priority. * * Clock can be driven by any of the following (CKP selects clock polarity): - - - One of the four high performance hardwired fast clocks (HCLKs) One of the four routed clocks (CLKs) User signals
Global power-on clear (GCLR) and preset (GPSET), which drive each flip-flop on a chip-wide basis. - When the Global Set Fuse option in the Designer software is unchecked (by default), GCLR = 0 and GPSET =1 at device power-up. When the option is checked, GCLR = 1 and GPSET= 0. Both pins are pulled High when the device is in user mode.
*
* *
S0, S1, PSET, and CLR can be driven by routed clocks CLKE/F/G/H or user signals. DIN and S1 can be driven by user signals.
* * *
As with the C-cell, the configuration of the R-cell to perform various functions is handled automatically for the user through Actel's extensive macro library (please see Actel's Antifuse Macro Library Guide for a complete listing of available AX macros).
CKP
DIN(user signals) DCIN HCLKA/B/C/D CLKE/F/G/H Internal Logic
CLR GCLR
CKS
S1
Figure 2-31 * R-Cell
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S0
PSET GPSET
Y
2-47
Axcelerator Family FPGAs
Timing Models and Waveforms
D
tSUD CLK tRCO Q
tHD
tCPWHL
tCPWLH
tHASYN CLR tWASYN
tREASYN tCLR tHASYN tWASYN tREASYN
tPRESET PRESET tSUE E tHE
Figure 2-32 * R-Cell Delays
Timing Characteristics
Table 2-62 * R-Cell Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter R-Cell Propagation Delays tRCO tCLR tPRESET tSUD tSUE tHD tHE tWASYN tREASYN tHASYN tCPWHL tCPWLH Sequential Clock-to-Q Asynchronous Clear-to-Q Asynchronous Preset-to-Q Flip-Flop Data Input Set-Up Flip-Flop Enable Input Set-Up Flip-Flop Data Input Hold Flip-Flop Enable Input Hold Asynchronous Pulse Width Asynchronous Recovery Time Asynchronous Removal Time Clock Pulse Width High to Low Clock Pulse Width Low to High 0.42 0.40 0.43 0.10 0.00 0.47 0.46 0.67 0.23 0.23 0.23 0.26 0.00 0.00 0.48 0.10 0.00 0.55 0.54 0.77 0.27 0.27 0.27 0.30 0.00 0.00 0.57 0.10 0.00 0.90 0.31 0.31 0.31 0.35 0.00 0.00 ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
2 -4 8
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Axcelerator Family FPGAs
Buffer Module
Introduction
An additional resource inside each SuperCluster is the Buffer (B) module (Figure 1-4 on page 1-3). When a fanout constraint is applied to a design, the synthesis tool inserts buffers as needed. The buffer module has been added to the AX architecture to avoid logic duplication resulting from the hard fanout constraints. The router utilizes this logic resource to save area and reduce loading and delays on medium-to-high-fanout nets.
Timing Models and Waveforms
IN
OUT
Figure 2-33 * Buffer Module Timing Model
VCCA 50% IN VCCA OUT GND 50% tBFPD tBFPD 50% 50% GND
Figure 2-34 * Buffer Module Waveform
Timing Characteristics
Table 2-63 * Buffer Module Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
Buffer Module Propagation Delays tBFPD Any input to output Y 0.12 0.14 0.16 ns
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2-49
Axcelerator Family FPGAs
Routing Specifications
Routing Resources
The routing structure found in Axcelerator devices enables any logic module to be connected to any other logic module while retaining high performance. There are multiple paths and routing resources that can be used to route one logic module to another, both within a SuperCluster and elsewhere on the chip. There are four primary types of routing within the AX architecture: DirectConnect, CarryConnect, FastConnect, and Vertical and Horizontal Routing.
DirectConnect
DirectConnects provide a high-speed connection between an R-cell and its adjacent C-cell (Figure 2-35). This connection can be made from DCOUT of the C-cell to DCIN of the R-cell by configuring of the S1 line of the R-cell. This provides a connection that does not require an antifuse and has a delay of less than 0.1 ns.
Figure 2-35 * DirectConnect and CarryConnect
CarryConnect
CarryConnects are used to build carry chains for arithmetic functions (Figure 2-35). The FCO output of the right C-cell of a two-C-cell Cluster drives the FCI input of the left C-cell in the two-C-cell Cluster immediately below it. This pattern continues down both sides of each SuperCluster column. Similar to the DirectConnects, CarryConnects can be built without an antifuse connection. This connection has a delay of less than 0.1 ns from the FCO of one two-C-cell cluster to the FCI of the two-C-cell cluster immediately below it (see the "Carry-Chain Logic" on page 2-45 for more information).
then be routed through a single antifuse connection to drive the inputs of logic modules either within one SuperCluster or in the SuperCluster immediately below it.
Vertical and Horizontal Routing
Vertical and Horizontal Tracks provide both local and long distance routing (Figure 2-37 on page 2-51). These tracks are composed of both short-distance, segmented routing and across-chip routing tracks (segmented at core tile boundaries). The short-distance, segmented routing resources can be concatenated through antifuse connections to build longer routing tracks. These short-distance routing tracks can be used within and between SuperClusters or between modules of nonadjacent SuperClusters. They can be connected to the Output Tracks and to any logic module input (R-cell, C-cell, Buffer, and TX module). The across-chip horizontal and vertical routing provides long-distance routing resources. These resources interface with the rest of the routing structures through
FastConnect
For high-speed routing of logic signals, FastConnects can be used to build a short distance connection using a single antifuse (Figure 2-36 on page 2-51). FastConnects provide a maximum delay of 0.3 ns. The outputs of each logic module connect directly to the Output Tracks within a SuperCluster. Signals on the Output Tracks can
2 -5 0
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Axcelerator Family FPGAs
the RX and TX modules (Figure 2-37). The RX module is used to drive signals from the across-chip horizontal and vertical routing to the Output Tracks within the SuperCluster. The TX module is used to drive vertical and
horizontal across-chip routing from either short-distance horizontal tracks or from Output Tracks. The TX module can also be used to drive signals from vertical across-chip tracks to horizontal across-chip tracks and vice versa.
Figure 2-36 * FastConnect Routing
Figure 2-37 * Horizontal and Vertical Tracks
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2-51
Axcelerator Family FPGAs
Timing Characteristics
Table 2-64 * AX125 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425V, TJ = 70C '-2' Speed Parameter Predicted Routing Delays tDC tFC tRD1 tRD2 tRD3 tRD4 tRD5 tRD6 tRD7 tRD8 tRD16 tRD32 DirectConnect Routing Delay, FO1 FastConnect Routing Delay, FO1 Routing delay for FO1 Routing delay for FO2 Routing delay for FO3 Routing delay for FO4 Routing delay for FO5 Routing delay for FO6 Routing delay for FO7 Routing delay for FO8 Routing delay for FO16 Routing delay for FO32 0.11 0.35 0.35 0.38 0.43 0.48 0.55 0.64 0.79 0.88 1.49 2.32 0.12 0.39 0.40 0.43 0.48 0.55 0.62 0.72 0.89 0.99 1.69 2.63 0.15 0.46 0.47 0.51 0.57 0.64 0.73 0.85 1.05 1.17 1.99 3.10 ns ns ns ns ns ns ns ns ns ns ns ns Description Typical '-1' Speed Typical 'Std' Speed Typical Units
Table 2-65 * AX250 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425V, TJ = 70C '-2' Speed Parameter Predicted Routing Delays tDC tFC tRD1 tRD2 tRD3 tRD4 tRD5 tRD6 tRD7 tRD8 tRD16 tRD32 DirectConnect Routing Delay, FO1 FastConnect Routing Delay, FO1 Routing delay for FO1 Routing delay for FO2 Routing delay for FO3 Routing delay for FO4 Routing delay for FO5 Routing delay for FO6 Routing delay for FO7 Routing delay for FO8 Routing delay for FO16 Routing delay for FO32 0.11 0.35 0.39 0.41 0.48 0.56 0.60 0.84 0.90 1.00 2.17 3.55 0.12 0.39 0.45 0.46 0.55 0.63 0.68 0.96 1.02 1.13 2.46 4.03 0.15 0.46 0.53 0.54 0.64 0.75 0.80 1.13 1.20 1.33 2.89 4.74 ns ns ns ns ns ns ns ns ns ns ns ns Description Typical '-1' Speed Typical 'Std' Speed Typical Units
2 -5 2
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Axcelerator Family FPGAs
Table 2-66 * AX500 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425V, TJ = 70C '-2' Speed Parameter Predicted Routing Delays tDC tFC tRD1 tRD2 tRD3 tRD4 tRD5 tRD6 tRD7 tRD8 tRD16 tRD32 DirectConnect Routing Delay, FO1 FastConnect Routing Delay, FO1 Routing delay for FO1 Routing delay for FO2 Routing delay for FO3 Routing delay for FO4 Routing delay for FO5 Routing delay for FO6 Routing delay for FO7 Routing delay for FO8 Routing delay for FO16 Routing delay for FO32 0.11 0.35 0.39 0.41 0.48 0.56 0.60 0.84 0.90 1.00 2.17 3.55 0.12 0.39 0.45 0.46 0.55 0.63 0.68 0.96 1.02 1.13 2.46 4.03 0.15 0.46 0.53 0.54 0.64 0.75 0.80 1.13 1.20 1.33 2.89 4.74 ns ns ns ns ns ns ns ns ns ns ns ns Description Typical '-1' Speed Typical 'Std' Speed Typical Units
Table 2-67 * AX1000 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425V, TJ = 70C '-2' Speed Parameter Predicted Routing Delays tDC tFC tRD1 tRD2 tRD3 tRD4 tRD5 tRD6 tRD7 tRD8 tRD16 tRD32 DirectConnect Routing Delay, FO1 FastConnect Routing Delay, FO1 Routing delay for FO1 Routing delay for FO2 Routing delay for FO3 Routing delay for FO4 Routing delay for FO5 Routing delay for FO6 Routing delay for FO7 Routing delay for FO8 Routing delay for FO16 Routing delay for FO32 0.12 0.35 0.45 0.53 0.56 0.63 0.73 0.99 1.02 1.48 2.57 4.24 0.13 0.39 0.51 0.60 0.63 0.71 0.82 1.13 1.15 1.68 2.91 4.81 0.15 0.46 0.60 0.71 0.74 0.84 0.97 1.32 1.36 1.97 3.42 5.65 ns ns ns ns ns ns ns ns ns ns ns ns Description Typical '-1' Speed Typical 'Std' Speed Typical Units
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Axcelerator Family FPGAs
Table 2-68 * AX2000 Predicted Routing Delays Worst-Case Commercial Conditions VCCA = 1.425V, TJ = 70C '-2' Speed Parameter Predicted Routing Delays tDC tFC tRD1 tRD2 tRD3 tRD4 tRD5 tRD6 tRD7 tRD8 tRD16 tRD32 DirectConnect Routing Delay, FO1 FastConnect Routing Delay, FO1 Routing delay for FO1 Routing delay for FO2 Routing delay for FO3 Routing delay for FO4 Routing delay for FO5 Routing delay for FO6 Routing delay for FO7 Routing delay for FO8 Routing delay for FO16 Routing delay for FO32 0.12 0.35 0.50 0.59 0.70 0.76 0.98 1.48 1.65 1.73 2.58 4.24 0.13 0.39 0.56 0.67 0.80 0.87 1.11 1.68 1.87 1.96 2.92 4.81 0.15 0.46 0.66 0.79 0.94 1.02 1.31 1.97 2.20 2.31 3.44 5.65 ns ns ns ns ns ns ns ns ns ns ns ns Description Typical '-1' Speed Typical 'Std' Speed Typical Units
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Global Resources
One of the most important aspects of any FPGA architecture is its global resources or clocks. The Axcelerator family provides the user with flexible and easy-to-use global resources, without the limitations normally found in other FPGA architectures. The AX architecture contains two types of global resources, the HCLK (hardwired clock) and CLK (routed clock). Every Axcelerator device is provided with four HCLKs and four CLKs for a total of eight clocks, regardless of device density.
Hardwired Clocks
The hardwired (HCLK) is a low-skew network that can directly drive the clock inputs of all sequential modules (R-cells, I/O registers, and embedded RAM/FIFOs) in the device with no antifuse in the path. All four HCLKs are available everywhere on the chip.
Timing Characteristics
Table 2-69 * AX125 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter tHCKL tHCKH tHPWH tHPWL tHCKSW tHP tHMAX Description Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 1.15 870 0.58 0.52 0.06 1.31 763 Min. Max. 3.02 3.03 0.65 0.59 0.07 1.54 649 Dedicated (Hardwired) Array Clock Networks 3.44 3.46 0.77 0.69 0.08 4.05 4.06 ns ns ns ns ns ns MHz '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
Table 2-70 * AX250 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter tHCKL tHCKH tHPWH tHPWL tHCKSW tHP tHMAX Description Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 1.15 870 0.58 0.52 0.06 1.31 763 Min. Max. 2.57 2.61 0.65 0.59 0.07 1.54 649 Dedicated (Hardwired) Array Clock Networks 2.93 2.97 0.77 0.69 0.08 3.45 3.50 ns ns ns ns ns ns MHz '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
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Table 2-71 * AX500 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKL tHCKH tHPWH tHPWL tHCKSW tHP tHMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 1.15 870 0.58 0.52 0.06 1.31 763 2.35 2.44 0.65 0.59 0.07 1.54 649 2.68 2.79 0.77 0.69 0.08 3.15 3.27 ns ns ns ns ns ns MHz
Table 2-72 * AX1000 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKL tHCKH tHPWH tHPWL tHCKSW tHP tHMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 1.15 870 0.58 0.52 0.06 1.31 763 3.02 3.03 0.65 0.59 0.07 1.54 649 3.44 3.46 0.77 0.69 0.08 4.05 4.06 ns ns ns ns ns ns MHz
Table 2-73 * AX2000 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
Dedicated (Hardwired) Array Clock Networks tHCKL tHCKH tHPWH tHPWL tHCKSW tHP tHMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 1.15 870 0.58 0.52 0.06 1.31 763 3.02 3.03 0.65 0.59 0.07 1.54 649 3.44 3.46 0.77 0.69 0.08 4.05 4.06 ns ns ns ns ns ns MHz
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Routed Clocks
The routed clock (CLK) is a low-skew network that can drive the clock inputs of all sequential modules in the device (logically equivalent to the HCLK), but has the added flexibility in that it can drive the S0 (Enable), S1, PSET, and CLR input of a register (R-cells and I/O registers) as well as any of the inputs of any C-cell in the device. This allows CLKs to be used not only as clocks, but also for other global signals or high fanout nets. All four CLKs are available everywhere on the chip.
Timing Characteristics
Table 2-74 * AX125 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
Routed Array Clock Networks tRCKL tRCKH tRPWH tRPWL tRCKSW tRP tRMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 1.15 870 0.57 0.52 0.35 1.31 763 3.08 3.13 0.64 0.59 0.39 1.54 649 3.50 3.56 0.75 0.69 0.46 4.12 4.19 ns ns ns ns ns ns MHz
Table 2-75 * AX250 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
Routed Array Clock Networks tRCKL tRCKH tRPWH tRPWL tRCKSW tRP tRMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 1.15 870 0.57 0.52 0.35 1.31 763 2.52 2.59 0.64 0.59 0.39 1.54 649 2.87 2.95 0.75 0.69 0.46 3.37 3.47 ns ns ns ns ns ns MHz
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Table 2-76 * AX500 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
Routed Array Clock Networks tRCKL tRCKH tRPWH tRPWL tRCKSW tRP tRMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 1.15 870 0.57 0.52 0.35 1.31 763 2.31 2.44 0.64 0.59 0.39 1.54 649 2.63 2.78 0.75 0.69 0.46 3.09 3.27 ns ns ns ns ns ns MHz
Table 2-77 * AX1000 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
Routed Array Clock Networks tRCKL tRCKH tRPWH tRPWL tRCKSW tRP tRMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 1.15 870 0.57 0.52 0.35 1.31 763 3.08 3.13 0.64 0.59 0.39 1.54 649 3.50 3.56 0.75 0.69 0.46 4.12 4.19 ns ns ns ns ns ns MHz
Table 2-78 * AX2000 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
Routed Array Clock Networks tRCKL tRCKH tRPWH tRPWL tRCKSW tRP tRMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 1.15 870 0.57 0.52 0.35 1.31 763 3.08 3.13 0.64 0.59 0.39 1.54 649 3.50 3.56 0.75 0.69 0.46 4.12 4.19 ns ns ns ns ns ns MHz
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Global Resource Distribution
At the root of each global resource is a PLL. There are two groups of four PLLs for every device. One group, located at the center of the north edge (in the I/O ring) of the chip, sources the four HCLKs. The second group, located at the center of the south edge (again in the I/O ring), sources the four CLKs (Figure 2-38). Regardless of the type of global resource, HCLK or CLK, each of the eight resources reach the ClockTileDist (CTD) Cluster located at the center of every core tile with zero skew. From the ClockTileDist Cluster, all four HCLKs and four CLKs are distributed through the core tile (Figure 239).
PLL PN
PLL PN
PLL PN
PLL PN
PLL Cluster
HCLKA
HCLKB
HCLKC HCLKD
CLKE
CLKF
CLKG
CLKH
PLL Cluster
PN PLL
Figure 2-38 * PLL Group
PN PLL
PN PLL
PN PLL
HCLK
PLL Group
CLK
ClockTileDist Cluster
4
4
PLL Group
Figure 2-39 * Example of HCLK and CLK Distributions on the AX2000
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The ClockTileDist Cluster contains an HCLKMux (HM) module for each of the four HCLK trees and a CLKMux (CM) module for each of the CLK trees. The HCLK branches then propagate horizontally through the middle of the core tile to HCLKColDist (HD) modules in every SuperCluster column. The CLK branches propagate
vertically through the center of the core tile to CLKRowDist (RD) modules in every SuperCluster row. Together, the HCLK and CLK branches provide for a lowskew global fanout within the core tile (Figure 2-40 and Figure 2-41).
Figure 2-40 * CTD, CD, and HD Module Layout
Figure 2-41 * HCLK and CLK Distribution within a Core Tile
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The HM and CM modules can select between: * * The HCLK or CLK source respectively A local signal routed on generic routing resources
CLKINT and HCLKINT
CLKINT (HCLKINT) is used to access the CLK (HCLK) resource internally from the user signals (Figure 2-43).
This allows each core tile to have eight clocks independent of the other core tiles in the device. Both HCLK and CLK are segmentable, meaning that individual branches of the global resource can be used independently. Like the HM and CM modules, the HD and RD modules can select between: * * The HCLK or CLK source from the HM or CM module respectively A local signal routed on generic routing resources
Logic CLKINT HCLKINT
Figure 2-43 * CLKINT and HCLKINT
Clock Network
PLLRCLK and PLLHCLK
PLLRCLK (PLLHCLK) is used to drive global resource CLK (HCLK) from a PLL (Figure 2-44).
The AX architecture is capable of supporting a large number of local clocks - 24 segments per HCLK driving north-south and 28 segments per CLK driving east-west per core tile. Actel's Designer software's place-and-route takes advantage of the segmented clock structure found in Axcelerator devices by turning off any unused clock segments. This results in not only better performance but also lower power consumption.
RefCLK PLL FB
CLK1 CLK2 PLLRCLK PLLHCLK
Clock Network
Global Resource Access Macros
Global resources can be driven by one of three sources: external pad(s), an internal net, or the output of a PLL. These connections can be made by using one of three types of macros: CLKBUF, CLKINT, and PLLCLK.
Figure 2-44 * PLLRCLK and PLLHCLK
Using Global Resources with PLLs
Each global resource has an associated PLL at its root. For example, PLLA can drive HCLKA, PLLE can drive CLKE, etc. (Figure 2-45 on page 2-62). In addition, each clock pin of the package can be used to drive either its associated global resource or PLL. For example, package pins CLKEP and CLKEN can drive either the RefCLK input of PLLE or CLKE. There are two macros required when interfacing the embedded PLLs with the global resources: PLLINT and PLLOUT.
CLKBUF and HCLKBUF
CLKBUF (HCLKBUF) is used to drive a CLK (HCLK) from external pads. These macros can be used either generically or with the specific I/O standard desired (e.g. CLKBUF_LVCMOS25, HCLKBUF_LVDS, etc.) (Figure 2-42).
PLLINT
P Clock Network CLKBUF HCLKBUF
This macro is used to drive the RefCLK input of the PLL internally from user signals.
PLLOUT
N
Figure 2-42 * CLKBUF and HCLKBUF
This macro is used to connect either the CLK1 or CLK2 output of a PLL to the regular routing network (Figure 246 on page 2-62).
Package pins CLKEP and CLKEN are associated with CLKE; package pins HCLKAP and HCLKAN are associated with HCLKA, etc. Note that when CLKBUF (HCLKBUF) is used with a single-ended I/O standard, it must be tied to the Ppad of the CLK (HCLK) package pin. In this case, the CLK (HCLK) N-pad can be used for user signals.
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Implementation Example:
Figure 2-47 shows a complex clock distribution example. The reference clock (RefCLK) of PLLE is being sourced from non-clock signal pins (INBUF to PLLINT). The CLK1 output of PLLE is being fed to the RefCLK input of PLLF. The CLK2 output of PLLE is driving logic (via PLLOUT). In turn, this logic is driving the global resource CLKE. PLLF is driving both CLKF and CLKG global resources.
HCLKAP RefCLK PLLA HCLKAN FB CLK2 PLLHCLK CLK1 HCLKA Network
Figure 2-45 * Example of HCLKA driven from a PLL with External Clock Source
PLLINT Logic RefCLK PLLA FB CLK2 CLK1 PLLHCLK HCLKA Network
Logic PLLOUT
Figure 2-46 * Example of PLLINT and PLLOUT Usage
Non-Clock Pins P PLLRCLK N RefCLK PLLE FB CLK2 PLLOUT Logic CLKINT CLKE CLK1
INBUF
PLLINT
PLLRCLK RefCLK PLLF FB CLK2 PLLRCLK CLKG CLK1 CLKF
Figure 2-47 * Complex Clock Distribution Example
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Axcelerator Clock Management System
Introduction
Each member of the Axcelerator family contains eight phase-locked loop (PLL) blocks which perform the following functions: * * * * * * * * * Programmable Delay (32 steps of 250 ps) Clock Skew Minimization Clock Frequency Synthesis Input Frequency Range - 14 to 200 MHz Output Frequency Range - 20 MHz to 1 GHz Output Duty Cycle Range - 45% to 55% Maximum Long-Term (whichever is greater) Jitter - 1% or 100ps southern edge. The northern group is associated with the four HCLK networks (e.g. PLLA can drive HCLKA), while the southern group is associated with the four CLK networks (e.g. PLLE can drive CLKE). Each PLL cell is connected to two I/O pads and a PLL Cluster that interfaces with the FPGA core. Figure 2-48 illustrates a PLL block. The VCCPLL pin should be connected to a 1.5V power supply through a 250 resistor. Furthermore, 0.1 F and 10 F decoupling capacitors should be connected across the VCCPLL and VCOMPPLL pins. Note: The VCOMPPLL pin should never be grounded (Figure 2-2 on page 2-9)! The I/O pads associated with the PLL can also be configured for regular I/O functions except when it is used as a clock buffer. The I/O pads can be configured in all the modes available to the regular I/O pads in the same I/O bank. In particular, the [H]CLKxP pad can be configured as a differential pair, single-ended, or voltage-referenced standard. The [H]CLKxN pad can only be used as a differential pair with [H]CLKxP. The block marked "/i Delay Match" is a fixed delay equal to that of the i divider. The "/j Delay Match" block has the same function as its j divider counterpart.
Each PLL has the following key features:
Maximum Short-Term Jitter - 50ps + 1% of Output Frequency Maximum Acquisition Time (lock) - 20s
Physical Implementation
The eight PLL blocks are arranged in two groups of four. One group is located in the center of the northern edge of the chip, while the second group is centered on the
DIVJ PowerDown RefCLK Delay Line 6 Lock
/i Delay Match PLL /j CLK1
FB Delay Line /i
/j Delay Match 5 DelayLine 6 DIVJ 3 Osc
CLK2
FBMuxSel
LowFreq
Figure 2-48 * PLL Block Diagram
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Functional Description
Figure 2-48 on page 2-63 illustrates a block diagram of the PLL. The PLL contains two dividers, i and j, that allow frequency scaling of the clock signal: * The i divider in the feedback path allows multiplication of the input clock by integer factors ranging from 1 to 64, and the resultant frequency is available at the output of the PLL block. * The j divider divides the PLL output by integer factors ranging from 1 to 64, and the divided clock is available at CLK1. * The two dividers together can implement any combination of multiplication and division up to a maximum frequency of 1 GHz on CLK1. Both the CLK1 and CLK2 outputs have a fixed 50/50 duty cycle. * The output frequencies of the two clocks are given by the following formulas (fREF is the reference clock frequency): fCLK1 = fREF * (DividerI) / (DividerJ)
EQ 2-4
*
CLK2 provides the PLL output directly--without division
The input and output frequency ranges are selected by LowFreq and Osc(2:0), respectively. These functions and their possible values are detailed in Table 2-79. The delay lines shown in Figure 2-48 on page 2-63 are programmable. The feedback clock path can be delayed (using the five DelayLine bits) relative to the reference clock (or vice versa) by up to 3.75 ns in increments of 250 ps. Table 2-79 describes the usage of these bits. The delay increments are independent of frequency, so this results in phase changes that vary with frequency. The delay value is highly dependent on VCC and the speed grade. Figure 2-49 on page 2-65 is a logical diagram of the various control signals to the PLL and shows how the PLL interfaces with the global and routing networks of the FPGA. Note that not all signals are user-accessible. These non-user-accessible signals are used by Actel's place-androute tool to control the configuration of the PLL. The user gains access to these control signals either based upon the connections built in the user's design or through the special macros (Table 2-83 on page 2-67) inserted into the design. For example, connecting the macro PLLOUT to CLK2 will control the OUTSEL signal.
fCLK2 = fREF * (DividerI)
EQ 2-5 Table 2-79 * PLL Interface Signals Signal Name
RefCLK FB PowerDown
Type
Input Input Input
User Accessible
Yes Yes Yes
Allowable Values
Feedback port for the PLL PLL power down control 0 1 PLL powered down PLL active
Function
Reference Clock for the PLL
DIVI[5:0] DIVJ[5:0] LowFreq
Input Input Input
Yes Yes Yes
1 to 64, in unsigned binary notation offset by -1 0 1
Sets value for feedback divider (multiplier) Sets value for CLK1 divider Input frequency range selector 50-200 MHz 14-50 MHz Output frequency range selector 400-1000 MHZ 200-400 MHZ 100-200 MHZ 50-100 MHZ 20-50 MHZ
Osc[2:0]
Input
Yes XX0 001 011 101 111
DelayLine[4:0]
Input
Yes
Clock Delay (positive/negative) in increments of 250 ps, with -15 to +15 (increments), in signed- maximum value of 3.75 ns and-magnitude binary representation Selects the source for the feedback input Selects the source for the reference clock Selects the source for the routed net output
FBMuxSel REFSEL OUTSEL
Input Input Input
No No No
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Table 2-79 * PLL Interface Signals (Continued) Signal Name
PLLSEL ROOTSEL Lock CLK1 CLK2
Type
Input Input Output Output Output
User Accessible
No No Yes Yes Yes
Allowable Values
Function
ROOTSEL & PLLSEL are used to select the source of the global clock network High value indicates PLL has locked PLL clock output PLL clock output
Note: If the input RefClk is taken outside its operating range, the outputs Lock, CLK1 and CLK2 are indeterminate.
REFSEL CLK1 (PLLn-1) [H]CLKINT [H]CLKxP I/O Core net CLK net PLL FBINT FB [H]CLKxN FBMuxSEL
Note: Not all signals are available to the user. Figure 2-49 * PLL Logical Interface
ROOTSEL CLKINT CLK1 (PLLn-1) RefCLK CLK1 0 1 2 3 PLLSEL 0 1 OUTSEL To PLLn+1 CLK Out (Routed net out pin)
[H]CLK
CLK2
PLL Configurations
The following rules apply to the different PLL inputs and outputs:
Regular, LVPECL, or LVDS IOPAD
Reference Clock
The RefCLK can be driven by (Figure 2-50): 1. Global routed clocks (CLKE/F/G/H) or user-created clock network 2. CLK1 output of an adjacent PLL 3. [H]CLKxP (single-ended or voltage-referenced) 4. [H]CLKxP/[H]CLKxN pair LVPECL or LVDS) (differential modes like
Non-clock Pins P N
INBUF RefCLK PLL
Any macro from the core, except HCLK nets
RefCLK Logic
PLL
Feedback Clock
The feedback clock can be driven by (Figure 2-51 on page 2-66): 1. Global routed clocks (CLKE/F/G/H) or user-created clock network 2. External [H]CLKxP/N I/O pad(s) from the adjacent PLL cell 3. An internal signal from the PLL block
For cascading
PLL
CLK1 RefCLK
PLL
Figure 2-50 * Reference Clock Connections
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Table 2-81 * North PLL Connections
PLLOUT/PLLRCLK FB PLL
CLK1 HCLK1 HCLK1 HCLK2 HCLK2 HCLK2 HCLK2 Unused Unused Unused Unused Routed net Routed net Both HCLK1 and HCLK2 Both HCLK1 and HCLK2 Both HCLK1 and routed net Both HCLK2 and routed net Both HCLK2 and routed net Routed net Unused HCLK1 Routed net
CLK2
Any macro except HCLK macros FB PLL
Figure 2-51 * Feedback Clock Connections
Both HCLK1 and routed net Unused HCLK1 Routed net Both HCLK1 and routed net Unused HCLK1 Unused Routed net Unused Unusable HCLK1 Unused
CLK1 and CLK2
Both PLL outputs, CLK1 and CLK2, can be used to drive a global resource, an adjacent PLL RefCLK input, or a net in the FPGA core. Not all drive combinations are possible (Table 2-80).
Table 2-80 * PLL General Connections Rules CLK1 HCLK CLK HCLK Routed net output HCLK NONE CLK NONE HCLK CLK Routed net output HCLK NONE HCLK NONE CLK CLK2
HCLK1, HCLK2, and routed net Unusable Note: Designer software currently does not support all of these connections. Only exclusive connections where one output connects to a single net are supported at this time (e.g.CLK1 driving HCLK1, and HCLK2 is not supported). Table 2-82 * South PLL Connections CLK1 CLK1 CLK1 CLK2 CLK2 CLK2 CLK2 Unused Unused Unused Unused Routed net Routed net Both CLK1 and CLK2 Both CLK1 and CLK2 Both CLK1 and routed net Both CLK2 and routed net Both CLK2 and routed net CLK1, CLK2, and routed net Routed net Unused CLK1 Routed net Both CLK1 and routed net Unused CLK1 Routed net Both CLK1 and routed net Unused CLK1 Unused Routed net Unused Unusable CLK1 Unused Unusable CLK2
Note: The PLL outputs remain Low when REFCLK is constant (either Low or High).
Restrictions on CLK1 and CLK2
* When both are driving global resources, they must be driving the same type of global resource (i.e. either HCLK or CLK). Only one can drive a routed net at any given time.
*
Table 2-81 and Table 2-82 specify all the possible CLK1 and CLK2 connections for the north and south PLLs. HCLK1 and HCLK2 are used to denote the different HCLK networks when two are being driven at the same time by a single PLL (Note that HCLK1 is the primary clock resource associated with the PLL, and HCLK2 is the clock resource associated with the adjacent PLL). Likewise, CLK1 and CLK2 are used to denote the different CLK networks when two are being driven at the same time by a single PLL (Figure 2-48 on page 2-63).
Note: Designer software currently does not support all of these connections. Only exclusive connections where one output connects to a single net are supported at this time (e.g., CLK1 driving both CLK1 and CLK2 is not supported).
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Special PLL Macros
Table 2-83 shows the macros used to connect the RefCLK input and CLK1 and CLK2 outputs using the different routing resources.
Table 2-83 * PLL Special Macros Macro Name PLLINT PLLRCLK PLLHCLK PLLOUT Usage Connects RefCLK to a regular routed net or a pad. Connects CLK1 or CLK2 to the CLK network. Connects CLK1 or CLK2 to the HCLK network. Connects CLK1 or CLK2 to a regular routed net.
Table 2-84 * Electrical Specifications Parameter
Frequency Ranges Reference Frequency (min.) Reference Frequency (max.) OSC Frequency (min.) OSC Frequency (max.) Jitter Long-Term Jitter (max.) Long-Term Jitter (max.) Short-Term Jitter (max.) Acquisition Time (lock) from Cold Start Acquisition Time (max.)* Acquisition Time (max.)* Power Consumption Analog Supply Current (low freq.) Analog Supply Current (high freq.) Digital Supply Current (low freq.) Digital Supply Current (high freq.) Duty Cycle Minimum Output Duty Cycle Maximum Output Duty Cycle 45% 55% 200A 200A 0.5A/MHz 1A/MHz Current at minimum oscillator frequency Frequency-dependent current Current at maximum oscillator frequency, unloaded Frequency-dependent current 400 cycles 1.5 s Period of low reference clock frequencies High reference clock frequencies 1% 100ps 50ps+1% Percentage of period, low reference clock frequencies High reference clock frequencies Percentage of output frequency 14 MHz 200 MHz 20 MHz 1 GHz Lowest input frequency Highest input frequency Lowest output frequency Highest output frequency
Value
Notes
Note: *The lock bit remains Low until RefCLK reaches the minimum input frequency.
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User Flow
There are two methods of including a PLL in a design: * The recommended method of using a PLL is to create custom PLL blocks using Actel's macro generator, SmartGen, that can be instantiated in a design. * The alternative method is to instantiate one of the generic library primitives (PLL or PLLFB) into either a schematic or HDL netlist, using inverters for polarity control and tying all unused address and data bits to ground.
Timing Model
Lock CLK1 tPCLK* CLK
FB 6 6 5 3
CLK2
DividerI/DividerJ
Configuration Pins
Delay Line FBMux
Note: tPCLK is the delay in the clock signal Figure 2-52 * PLL Model
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Axcelerator Family FPGAs
Sample Implementations
Frequency Synthesis
Figure 2-53 illustrates an example where the PLL is used to multiply a 155.5 MHz external clock up to 622 MHz. Note that the same PLL schematic could use an external 350 MHz clock, which is divided down to 155 MHz by the FPGA internal logic. Figure 2-54 illustrates the PLL using both dividers to synthesize a 133 MHz output clock from a 155 MHz input reference clock. The input frequency of 155 MHz is multiplied by 6 and divided by 7, giving a CLK1 output frequency of 132.86 MHz. When dividers are used, a given ratio can be generated in multiple ways, allowing the user to stay within the operating frequency ranges of the PLL.
DividerJ 6
PowerDown
Lock
RefCLK 155.5 MHz Delay Line
/i Delay Match PLL /j CLK1
FB Delay Line /i /j Delay Match CLK2
622 MHz FBMuxSel 5 DelayLine 6 DividerI /4
Figure 2-53 * Using the PLL 155.5 MHz In, 622 MHz Out
LowFreq
3 Osc
/7 PowerDown DividerJ 6
Lock
RefCLK 155 MHz
Delay Line
/i Delay Match
155 MHz 930 MHz
132.8 MHz PLL /j CLK1
FB Delay Line /i 155 MHz Yes /j Delay Match CLK2
5 FBMuxSel DelayLine
6 DividerI /6 LowFreq
3 Osc
Figure 2-54 * Using the PLL 155 MHz In, 133 MHz Out
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Axcelerator Family FPGAs
Adjustable Clock Delay
Figure 2-55 illustrates using the PLL to delay the reference clock by employing one of the adjustable delay lines. In this case, the output clock is delayed relative to the reference clock. Delaying the reference clock relative to the output clock is accomplished by using the delay line in the feedback path.
DividerJ 6 Lock RefCLK 133 MHz
PowerDown
Delay Line
/i Delay Match PLL /j CLK1
FB Delay Line /j /j Delay Match CLK2
133 MHz
5 FBMuxSel DelayLine
6 DividerI /1 LowFreq
3 Osc
Figure 2-55 * Using the PLL Delaying the Reference Clock
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Axcelerator Family FPGAs
Clock Skew Minimization
Figure 2-56 indicates how feedback from the clock network can be used to create minimal skew between the distributed clock network and the input clock. The input clock is fed to the reference clock input of the PLL. The output clock (CLK2) feeds a routed clock network. The feedback input to the PLL uses a clock input delayed by a routing network. The PLL then adjusts the phase of the input clock to match the delayed clock, thus providing nearly zero effective skew between the two clocks. Refer to Actel's Axcelerator Family PLL and Clock Management application note for more information.
PowerDown RefCLK Input Clock 133 MHz FB Delay Line /i Delay Line /i Delay Match PLL 133 MHz
DividerJ 6 Lock
CLK1 /j CLK2
/i Delay Match
133 MHz 5 DelayLine 6 DividerI /1 3 Osc
FBMuxSel
LowFreq
Q
SET
D
QCLR
Clock Network
Figure 2-56 * Using the PLL for Clock Deskewing
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Axcelerator Family FPGAs
Embedded Memory
The AX architecture provides extensive, high-speed memory resources to the user. Each 4,608 bit block of RAM contains its own embedded FIFO controller, allowing the user to configure each block as either RAM or FIFO. To meet the needs of high performance designs, the memory blocks operate in synchronous mode for both read and write operations. However, the read and write clocks are completely independent, and each may operate up to and above 500 MHz. No additional core logic resources are required to cascade the address and data buses when cascading different RAM blocks. Dedicated routing runs along each column of RAM to facilitate cascading. The AX memory block includes dedicated FIFO control logic to generate internal addresses and external flag logic (FULL, EMPTY, AFULL, AEMPTY). Since read and write operations can occur asynchronously to one another, special control circuitry is included to prevent metastability, overflow, and underflow. A block diagram of the memory module is illustrated in Figure 2-57. During RAM operation, read (RA) and write (WA) addresses are sourced by user logic and the FIFO controller is ignored. In FIFO mode, the internal addresses are generated by the FIFO controller and routed to the RAM array by internal MUXes. Enables with programmable polarity are provided to create upper address bits for cascading up to 16 memory blocks. When cascading memory blocks, the bussed signals WA, WD, WEN, RA, RD, and REN are internally linked to eliminate external routing congestion.
Table 2-85 * Memory Block WxD Options Data-word (in bits) 1 2 4 9 18 36 Depth 4,096 2,048 1,024 512 256 128 Address Bus RA/WA[11:0] RA/WA[10:0] RA/WA[9:0] RA/WA[8:0] RA/WA[7:0] RA/WA[6:0] Data Bus RD/WD[0] RD/WD[1:0] RD/WD[3:0] RD/WD[8:0] RD/WD[17:0] RD/WD[35:0]
RA [K:0] REN RCLK WD [(M-1):0] WA [J:0] WEN WCLK PIPE RW [2:0] WW [2:0]
RD [(N-1):0]
Figure 2-57 * Axcelerator Memory Module
RAM
Each memory block consists of 4,608 bits that can be organized as 128x36, 256x18, 512x9, 1kx4, 2kx2, or 4kx1 and are cascadable to create larger memory sizes. This allows built-in bus width conversion (Table 2-85). Each block has independent read and write ports which enable simultaneous read and write operations.
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Axcelerator Family FPGAs
Clocks
The RCLK and the WCLK have independent source polarity selection and can be sourced by any global or local signal.
The D x W different configurations are: 128 x 36, 256 x 18, 512 x 9, 1k x 4, 2k x 2, and 4k x 1. The allowable RW and WW values are shown in Table 2-87. When widths of one, two, and four are selected, the ninth bit is unused. For example, when writing nine-bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addressable for read operations. The ninth bit is not accessible. Conversely, when writing four-bit values and reading nine-bit values, the ninth bit of a read operation will be undefined. Note that the RAM blocks employ little-endian byte order for read and write operations.
RAM Configurations
The AX architecture allows the read side and write side of RAMs to be organized independently, allowing for bus conversion. For example, the write side can be set to 256x18 and the read side to 512x9. Both the write width and read width for the RAM blocks can be specified independently and changed dynamically with the WW (write width) and RW (read width) pins.
Table 2-86 * RAM Signal Description Signal WCLK WA[J:0] WD[M-1:0] RCLK RA[K:0] RD[N-1:0] REN WEN RW[2:0] WW[2:0] Pipe Direction Input Input Input Input Input Output Input Input Input Input Input
Description Write clock (can be active on either edge). Write address bus.The value J is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for J is from 6 to15. Write data bus. The value M is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. Read clock (can be active on either edge). Read address bus. The value K is dependent on the RAM configuration and the number of cascaded memory blocks. The valid range for K is from 6 to 15. Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. Read enable. When this signal is valid on the active edge of the clock, data at location RA will be driven onto RD. Write enable. When this signal is valid on the active edge of the clock, WD data will be written at location WA. Width of the read operation dataword. Width of the write operation dataword. Sets the pipe option to be on or off.
Table 2-87 * Allowable RW and WW Values RW(2:0) 000 001 010 011 100 101 11x WW(2:0) 000 001 010 011 100 101 11x DxW 4k x 1 2k x 2 1k x 4 512 x 9 256 x 18 128 x 36 reserved
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Axcelerator Family FPGAs
Modes of Operation
There are two read modes and one write mode: * * * Read Nonpipelined (synchronous - one clock edge) Read Pipelined (synchronous - two clock edges) Write (synchronous - one clock edge) higher frequency. The read-address is registered on the read-port active-clock edge, and the read data is registered and appears at RD after the second read clock edge. Setting the PIPE to ON enables this mode. On the write active-clock edge, the write data are written into the SRAM at the write address when WEN is high. The setup time of the write address, write enables, and write data are minimal with respect to the write clock. Write and read transfers are described with timing requirements beginning in "Timing Characteristics".
In the standard read mode, new data is driven onto the RD bus in the clock cycle immediately following RA and REN valid. The read address is registered on the readport active-clock edge and data appears at read-data after the RAM access time. Setting the PIPE to OFF enables this mode. The pipelined mode incurs an additional clock delay from address to data, but enables operation at a much
Timing Characteristics
WD
RD
WA WCLK WEN
RA RCLK REN
Figure 2-58 * SRAM Model
tWCKP
tWCKH
tWCKL
WCLK tWxxSU WA<11:0>, WD<35:0>, WEN<4:0> tWxxHD
Figure 2-59 * RAM Write Timing Waveforms
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tRCKP
tRCKH
tRCKL
RCLK tRxxSU tRxxHD RA<11:0>, REN<4:0> tRCK2RD1 RD <35:0> tRCK2RD2
Figure 2-60 * RAM Read Timing Waveforms Table 2-88 * One RAM Block Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Write Mode tWDASU tWDAHD tWADSU tWADHD tWENSU tWENHD tWCKH tWCLK tWCKP Read Mode tRADSU tRADHD tRENSU tRENHD tRCK2RD1 tRCK2RD2 tRCLKH tRCLKL tRCKP Read Address Setup vs. RCLK Read Address Hold vs. RCLK Read Enable Setup vs. RCLK Read Enable Hold vs. RCLK RCLK-To-OUT (Pipelined) RCLK-To-OUT (Non-Pipelined) RCLK Minimum High Pulse Width RCLK Minimum Low Pulse Width RCLK Minimum Period 1.00 1.21 2.42 0.81 0.00 0.81 0.00 1.39 2.62 1.14 1.38 2.76 0.92 0.00 0.92 0.00 1.59 2.98 1.34 1.62 3.24 1.08 0.00 1.08 0.00 1.86 3.5 ns ns ns ns ns ns ns ns ns Write Data Setup vs. WCLK Write Data Hold vs. WCLK Write Address Setup vs. WCLK Write Address Hold vs. WCLK Write Enable Setup vs. WCLK Write Enable Hold vs. WCLK WCLK Minimum High Pulse Width WCLK Minimum Low Pulse Width WCLK Minimum Period 0.98 1.15 2.29 1.08 0.22 1.08 0.22 1.08 0.22 1.11 1.30 2.61 1.23 0.25 1.23 0.25 1.23 0.25 1.31 1.53 3.07 1.45 0.30 1.45 0.30 1.45 0.30 ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
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Axcelerator Family FPGAs
Table 2-89 * Two RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Write Mode tWDASU tWDAHD tWADSU tWADHD tWENSU tWENHD tWCKH tWCLK tWCKP Read Mode tRADSU tRADHD tRENSU tRENHD tRCK2RD1 tRCK2RD2 tRCLKH tRCLKL tRCKP Read Address Setup vs. RCLK Read Address Hold vs. RCLK Read Enable Setup vs. RCLK Read Enable Hold vs. RCLK RCLK-To-OUT (Pipelined) RCLK-To-OUT (Non-Pipelined) RCLK Minimum High Pulse Width RCLK Minimum Low Pulse Width RCLK Minimum Period 0.95 2.46 4.92 1.7 0.00 1.7 0.00 1.51 2.76 1.08 2.8 5.6 1.94 0.00 1.94 0.00 1.72 3.14 1.27 3.29 6.59 2.28 0.00 2.28 0.00 2.02 3.69 ns ns ns ns ns ns ns ns ns Write Data Setup vs. WCLK Write Data Hold vs. WCLK Write Address Setup vs. WCLK Write Address Hold vs. WCLK Write Enable Setup vs. WCLK Write Enable Hold vs. WCLK WCLK Minimum High Pulse Width WCLK Minimum Low Pulse Width WCLK Minimum Period 0.98 2.29 4.58 1.39 0.22 1.39 0.22 1.39 0.22 1.11 2.61 5.22 1.59 0.25 1.59 0.25 1.59 0.25 1.31 3.07 6.13 1.86 0.3 1.86 0.3 1.86 0.3 ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
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Axcelerator Family FPGAs
Table 2-90 * Four RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Write Mode tWDASU tWDAHD tWADSU tWADHD tWENSU tWENHD tWCKH tWCLK tWCKP Read Mode tRADSU tRADHD tRENSU tRENHD tRCK2RD1 tRCK2RD2 tRCLKH tRCLKL tRCKP Read Address Setup vs. RCLK Read Address Hold vs. RCLK Read Enable Setup vs. RCLK Read Enable Hold vs. RCLK RCLK-To-OUT (Pipelined) RCLK-To-OUT (Non-Pipelined) RCLK Minimum High Pulse Width RCLK Minimum Low Pulse Width RCLK Minimum Period 0.95 3.85 7.7 3.08 0.00 3.08 0.00 2.49 3.36 1.08 4.39 8.78 3.51 0.00 3.51 0.00 2.83 3.82 1.27 5.16 10.32 4.13 0.00 4.13 0.00 3.33 4.5 ns ns ns ns ns ns ns ns ns Write Data Setup vs. WCLK Write Data Hold vs. WCLK Write Address Setup vs. WCLK Write Address Hold vs. WCLK Write Enable Setup vs. WCLK Write Enable Hold vs. WCLK WCLK Minimum High Pulse Width WCLK Minimum Low Pulse Width WCLK Minimum Period 0.98 3.27 6.53 2.37 0.22 2.37 0.22 2.37 0.22 1.11 3.72 7.44 2.7 0.25 2.7 0.25 2.7 0.25 1.31 4.37 8.75 3.17 0.3 3.17 0.3 3.17 0.3 ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
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Axcelerator Family FPGAs
Table 2-91 * Eight RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Write Mode tWDASU tWDAHD tWADSU tWADHD tWENSU tWENHD tWCKH tWCLK tWCKP Read Mode tRADSU tRADHD tRENSU tRENHD tRCK2RD1 tRCK2RD2 tRCLKH tRCLKL tRCKP Read Address Setup vs. RCLK Read Address Hold vs. RCLK Read Enable Setup vs. RCLK Read Enable Hold vs. RCLK RCLK-To-OUT (Pipelined) RCLK-To-OUT (Non-Pipelined) RCLK Minimum High Pulse Width RCLK Minimum Low Pulse Width RCLK Minimum Period 0.95 7.51 15.02 6.75 0.00 6.75 0.00 3.57 5.48 1.08 8.55 17.11 7.69 0.00 7.69 0.00 4.06 6.24 1.27 10.05 20.11 9.04 0.00 9.04 0.00 4.77 7.34 ns ns ns ns ns ns ns ns ns Write Data Setup vs. WCLK Write Data Hold vs. WCLK Write Address Setup vs. WCLK Write Address Hold vs. WCLK Write Enable Setup vs. WCLK Write Enable Hold vs. WCLK WCLK Minimum High Pulse Width WCLK Minimum Low Pulse Width WCLK Minimum Period 0.98 6.68 13.35 5.78 0.22 5.78 0.22 5.78 0.22 1.11 7.6 15.21 6.58 0.25 6.58 0.25 6.58 0.25 1.31 8.94 17.88 7.74 0.3 7.74 0.3 7.74 0.3 ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
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Table 2-92 * Sixteen RAM Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter Write Mode tWDASU tWDAHD tWADSU tWADHD tWENSU tWENHD tWCKH tWCLK tWCKP Read Mode tRADSU tRADHD tRENSU tRENHD tRCK2RD1 tRCK2RD2 tRCLKH tRCLKL tRCKP Read Address Setup vs. RCLK Read Address Hold vs. RCLK Read Enable Setup vs. RCLK Read Enable Hold vs. RCLK RCLK-To-OUT (Pipelined) RCLK-To-OUT (Non-Pipelined) RCLK Minimum High Pulse Width RCLK Minimum Low Pulse Width RCLK Minimum Period 0.95 18.75 37.5 18.13 0.00 18.13 0.00 12.71 13.91 1.08 21.36 42.72 20.65 0.00 20.65 0.00 14.48 15.85 1.27 25.11 50.22 24.27 0.00 24.27 0.00 17.03 18.63 ns ns ns ns ns ns ns ns ns Write Data Setup vs. WCLK Write Data Hold vs. WCLK Write Address Setup vs. WCLK Write Address Hold vs. WCLK Write Enable Setup vs. WCLK Write Enable Hold vs. WCLK WCLK Minimum High Pulse Width WCLK Minimum Low Pulse Width WCLK Minimum Period 0.98 17.44 34.87 16.54 0.22 16.54 0.22 16.54 0.22 1.11 19.86 39.73 18.84 0.25 18.84 0.25 18.84 0.25 1.31 23.35 46.7 22.15 0.3 22.15 0.3 22.15 0.3 ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
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Axcelerator Family FPGAs
FIFO
Every memory block has its own embedded FIFO controller. Each FIFO block has one read port and one write port. This embedded FIFO controller uses no internal FPGA logic and features: * * * Glitch-free FIFO Flags Gray-code address counters/pointers to prevent metastability problems Overflow and underflow control * The FIFO block offers programmable almost-empty (AEMPTY) and almost-full (AFULL) flags as well as EMPTY and FULL flags (Figure 2-61): * The FULL flag is synchronous to WCLK. It allows the FIFO to inhibit writing when full. The EMPTY flag is synchronous to RCLK. It allows the FIFO to inhibit reading at the empty condition.
Both ports are configurable in various sizes from 4k x 1 to 128 x 36, similar to the RAM block size. Each port is fully synchronous. Read and write operations can be completely independent. Data on the appropriate WD pins are written to the FIFO on every active WCLK edge as long as WEN is high. Data is read from the FIFO and output on the appropriate RD pins on every active RCLK edge as long as REN is asserted.
Gray code counters are used to prevent metastability problems associated with flag logic. The depth of the FIFO is dependent on the data width and the number of memory blocks used to create the FIFO. The write operations to the FIFO are synchronous with respect to the WCLK, and the read operations are synchronous with respect to the RCLK. The FIFO block may be reset to the empty state.
RD [n-1:0] WD RCLK WCLK WD [n-1:0] RCLK WCLK RA [J:0] WA [J:0] REN WEN
RD
RAM
DEPTH[3:0]
=
FULL AFULL
>
AFVAL SUB 16
AEMPTY
AEVAL >=
FWEN CLR
CNT 16 E
=
EMPTY
Figure 2-61 * Axcelerator RAM with Embedded FIFO Controller
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WIDTH[2:0]
FREN
CNT 16 E
RW[2:0] WW[2:0]
PIPE
Axcelerator Family FPGAs
FIFO Flag Logic
The FIFO is user configurable into various DEPTHs and WIDTHs. Figure 2-62 shows the FIFO address counter details. * * * Bits 11 to 5 are active for all modes. As the data word size is reduced, more leastsignificant bits are added to the address. As the number of cascaded blocks increases, the number of significant bits in the address increases. RAM block, whereas bits 13 and 12 will be used to specify the RAM block. The AFULL and AEMPTY flag threshold values are programmable. The threshold values are AFVAL and AEVAL, respectively. Although the trigger threshold for each flag is defined with eight bits, the effective number of threshold bits in the comparison depends on the configuration. The effective number of threshold bits corresponds to the range of active bits in the FIFO address space (Table 2-93).
For example, if four blocks are cascaded as a 1kx16 FIFO with each block having a 1kx4 aspect ratio, bits 11 to 2 of the address will be used to specify locations within each
FIFO Address Counters
Mode when Active Cas 16 blks Cas 8 blks Cas 4 blks Cas 2 blks Counter Bits CNTR [15] activate CNTR [14] activate CNTR [13] activate CNTR [12] activate FIFO Address Alignment of Threshold bits
R/W EN[3] R/W EN[2] R/W EN[1] R/W EN[0]
AEVAL/AFVAL[7] AEVAL/AFVAL[6] AEVAL/AFVAL[5] AEVAL/AFVAL[4] AEVAL/AFVAL[3:0] not compared not compared not compared not compared not compared not compared CNTR [15:0] [12:W] [13:W]
128x36 256x18 512x9 1kx4 2kx2 4kx1
[15:W] [14:W]
by 36
R/W ADD[11:8] CNTR [11:5] always active R/W ADD[7:5] CNTR [4] activate CNTR [3] activate CNTR [2] activate CNTR [1] activate CNTR [0] activate R/W ADD[4] R/W ADD[3] R/W ADD[2] R/W ADD[1] R/W ADD[0]
[11:5] [11:4] [11:3] [11:2] [11:1] [11:0]
by 18 by 9 by 4 by 2 by 1
Variable Active Address Space >> REN [4:0], RAD [11:0] >> WEN [4:0], WAD [11:0]
Note: Inactive counter bits are set to zero. Figure 2-62 * FIFO Address Counters Table 2-93 * FIFO Flag Logic Mode Non-cascade Cascade 2 blocks Cascade 4 blocks Cascade 8 blocks Cascade 16 blocks Inactive AEVAL/AFVAL bits [7:4] [7:5] [7:6] [7] None Inactive DIFF bits (set to 0) [15:12] [15:13] [15:14] [15] None DIFF comparison to AFVAL/AEVAL DIFF[11:8] withAE/FVAL[3:0] DIFF[12:8] withAE/FVAL[4:0] DIFF[13:8] withAE/FVAL[5:0] DIFF[14:8] withAE/FVAL[6:0] DIFF[15:8] withAE/FVAL[7:0]
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Axcelerator Family FPGAs
Figure 2-63 illustrates flag generation. The Verilog codes for the flags are:
assign AF = (DIFF[15:0] >={AFVAL[7:0],8'b00000000})?1:0; assign AE = ({AEVAL[7:0],8'b00000000}>=DIFF[15:0])?1:0;
The number of DIFF-bits active depends on the configuration depth and width (Table 2-94).
ALMOST EMPTY and ALMOST FULL Logic
AEVAL [7:0], GND [7:0] (MSB....LSB) X Y
AEMPTY
WCLK
WCNTR [15:0]
16 DIFF [15:0]
X>=Y (16 bit)
RCLK
RCNTR [15:0]
16 X AFVAL [7:0], GND [7:0] (MSB....LSB) Y
AFULL
Figure 2-63 * ALMOST-EMPTY and ALMOST-FULL Logic Table 2-94 * Number of Available Configuration Bits Number of Blocks 1 2 2 4 4 4 8 8 8 8 16 16 16 16 16 Block DxW 1x1 1x2 2x1 1x4 2x2 4x1 1x8 2x4 4x2 8x1 1x16 2x8 4x4 8x2 16x1 Number of AEVAL/AFVAL Bits 4 4 5 4 5 6 4 5 6 7 4 5 6 7 8
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The active-high CLR pin is used to reset the FIFO to the empty state, which sets FULL and AFULL low, and EMPTY and AEMPTY high. Assuming that the EMPTY flag is not set, new data is read from the FIFO when REN is valid on the active edge of the clock. Write and read transfers are described with timing requirements in "Timing Characteristics" on page 2-85.
Overflow and Underflow Control
The counter MSB keeps track of the difference between the read address (RA) and the write address (WA). The EMPTY flag is set when the read and write addresses are equal. To prevent underflow, the write address is doublesampled by the read clock prior to comparison with the read address (part A in Figure 2-64). To prevent overflow, the read address is double-sampled by the write clock prior to comparison to the write address (part B in Figure 2-64).
Glitch Elimination
An analog filter is added to each FIFO controller to guarantee glitch-free FIFO-flag logic.
A
WA RA
B
RCLK RA
Figure 2-64 * Overflow and Underflow Control
=
EMPTY WCLK WA
=
FULL
FIFO Configurations
Unlike the RAM, the FIFO's write width and read width cannot be specified independently. For the FIFO, the write and read widths must be the same. The WIDTH pins are used to specify one of six allowable word widths, as shown in Table 2-95. The DEPTH pins allow RAM cells to be cascaded to create larger FIFOs. The four pins allow depths of 2, 4, 8, and 16 to be specified. Table 2-85 on page 2-72 describes the FIFO depth options for various data width and memory blocks.
Clock
As with RAM configuration, the RCLK and WCLK pins have independent polarity selection
Table 2-95 * FIFO Width Configurations WIDTH(2:0) 000 001 010 011 100 101 11x WxD 1 x 4k 2 x 2k 4 x 1k 9 x 512 18 x 256 36 x 128 reserved
Interface
Figure 2-65 shows a logic block diagram of the Axcelerator FIFO module.
DEPTH [3:0]
RD [35:0] FULL EMPTY AFULL AEMPTY
Cascading FIFO Blocks
FIFO blocks can be cascaded to create deeper FIFO functions. When building larger FIFO blocks, if the word width can be fractured in a multi-bit FIFO, the fractured word configuration is recommended over a cascaded configuration. For example, 256x36 can be configured as two blocks of 256x18. This should be taken into account when building the FIFO blocks manually. However, when using SmartGen, the user only needs to specify the depth and width of the necessary FIFO blocks. SmartGen automatically configures these blocks to optimize performance.
WIDTH [2:0] PIPE FREN RCLK AEVAL [7:0] AFVAL [7:0] WD [35:0] FWEN WCLK CLR
Figure 2-65 * FIFO Block Diagram
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Axcelerator Family FPGAs
Table 2-96 * FIFO Signal Description Signal WCLK FWEN WD[N-1:0] FULL AFULL AFVAL RCLK FREN RD[N-1:0] EMPTY AEMPTY AEVAL PIPE CLR DEPTH WIDTH Direction Input Input Input Output Output Input Input Input Output Output Output Input Input Input Input Input Write clock (active either edge). FIFO write enable. When this signal is asserted, the WD bus data is latched into the FIFO, and the internal write counters are incremented. Write data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. Active high signal indicating that the FIFO is FULL. When this signal is set, additional write requests are ignored. Active high signal indicating that the FIFO is AFULL. 8-bit input defining the AFULL value of the FIFO. Read clock (active either edge). FIFO read enable. Read data bus. The value N is dependent on the RAM configuration and can be 1, 2, 4, 9, 18, or 36. Empty flag indicating that the FIFO is EMPTY. When this signal is asserted, attempts to read the FIFO will be ignored. Active high signal indicating that the FIFO is AEMPTY. 8-bit input defining the almost-empty value of the FIFO. Sets the pipe option on or off. Active high clear input. Determines the depth of the FIFO and the number of FIFOs to be cascaded. Determines the width of the dataword / width of the FIFO, and the number of the FIFOs to be cascaded. Description
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Timing Characteristics
WD
RD AEMPTY EMPTY AFULL FULL
FWEN FREN WCLK RCLK
Clr
Figure 2-66 * FIFO Model
tWCKP
tWCKH
tWCKL
WCLK tWSU WD<35:0>, FWEN tCLR2HF tWHD
CLR tCLR2xF tCK2xF
EMPTY, AEMPTY, AFULL, FULL
Figure 2-67 * FIFO Write Timing
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Axcelerator Family FPGAs
tRCKP
tRCKH
tRCKL
RCLK FREN
tRSU
tRHD
tRCK2RD1 RD <35:0> tCLRHF
tRCK2RD2
CLR
tCLR2xF
tCK2xF
EMPTY, AEMPTY, AFULL, FULL
Figure 2-68 * FIFO Read Timing Table 2-97 * One FIFO Block Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter FIFO Module Timing tWSU tWHD tWCKH tWCKL tWCKP tRSU tRHD tRCKH tRCKL tRCKP tCLRHF tCLR2FF tCLR2AF tCK2FF tCK2AF tRCK2RD1 tRCK2RD2 Write Setup Write Hold WCLK High WCLK Low Minimum WCLK Period Read Setup Read Hold RCLK High RCLK Low Minimum RCLK period Clear High Clear-to-flag (EMPTY/FULL) Clear-to-flag (AEMPTY/AFULL) Clock-to-flag (EMPTY/FULL) Clock-to-flag (AEMPTY/AFULL) RCLK-To-OUT (Pipelined) RCLK-To-OUT (Non-Pipelined) 2.42 1.08 2.02 4.62 2.24 5.31 1.39 2.62 2.3 0.81 0.00 1.00 1.21 2.76 1.23 2.3 5.26 2.55 6.05 1.59 2.98 1.08 0.22 0.98 1.15 2.6 0.92 0.00 1.14 1.38 3.24 1.45 2.7 6.19 3 7.11 1.86 3.5 1.23 0.25 1.11 1.30 3.06 1.08 0.00 1.34 1.62 1.45 0.30 1.31 1.53 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
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Table 2-98 * Two FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter FIFO Module Timing tWSU tWHD tWCKH tWCKL tWCKP tRSU tRHD tRCKH tRCKL tRCKP tCLRHF tCLR2FF tCLR2AF tCK2FF tCK2AF tRCK2RD1 tRCK2RD2 Write Setup Write Hold WCLK High WCLK Low Minimum WCLK Period Read Setup Read Hold RCLK High RCLK Low Minimum RCLK period Clear High Clear-to-flag (EMPTY/FULL) Clear-to-flag (AEMPTY/AFULL) Clock-to-flag (EMPTY/FULL) Clock-to-flag (AEMPTY/AFULL) RCLK-To-OUT (Pipelined) RCLK-To-OUT (Nonpipelined) 4.92 1.08 2.02 4.62 2.24 5.31 1.51 2.76 4.58 1.7 0 0.95 2.46 5.6 1.23 2.3 5.26 2.55 6.05 1.72 3.14 1.39 0.22 0.98 2.29 5.22 1.94 0 1.08 2.8 6.58 1.45 2.7 6.19 3 7.11 2.02 3.69 1.59 0.25 1.11 2.61 6.14 2.28 0 1.27 3.29 1.86 0.3 1.31 3.07 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
Table 2-99 * Four FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter FIFO Module Timing tWSU tWHD tWCKH tWCKL tWCKP tRSU tRHD tRCKH tRCKL tRCKP tCLRHF tCLR2FF tCLR2AF tCK2FF tCK2AF tRCK2RD1 tRCK2RD2 Write Setup Write Hold WCLK High WCLK Low Minimum WCLK Period Read Setup Read Hold RCLK High RCLK Low Minimum RCLK period Clear High Clear-to-flag (EMPTY/FULL) Clear-to-flag (AEMPTY/AFULL) Clock-to-flag (EMPTY/FULL) Clock-to-flag (AEMPTY/AFULL) RCLK-To-OUT (Pipelined) RCLK-To-OUT (Nonpipelined) 7.7 1.08 2.02 4.62 2.24 5.31 2.49 3.36 6.54 3.08 0 0.95 3.85 8.78 1.23 2.3 5.26 2.55 6.05 2.83 3.82 2.37 0.22 0.98 3.27 7.44 3.51 0 1.08 4.39 10.32 1.45 2.7 6.19 3 7.11 3.33 4.5 2.7 0.25 1.11 3.72 8.74 4.13 0 1.27 5.16 3.17 0.3 1.31 4.37 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
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Table 2-100 * Eight FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter FIFO Module Timing tWSU tWHD tWCKH tWCKL tWCKP tRSU tRHD tRCKH tRCKL tRCKP tCLRHF tCLR2FF tCLR2AF tCK2FF tCK2AF tRCK2RD1 tRCK2RD2 Write Setup Write Hold WCLK High WCLK Low Minimum WCLK Period Read Setup Read Hold RCLK High RCLK Low Minimum RCLK period Clear High Clear-to-flag (EMPTY/FULL) Clear-to-flag (AEMPTY/AFULL) Clock-to-flag (EMPTY/FULL) Clock-to-flag (AEMPTY/AFULL) RCLK-To-OUT (Pipelined) RCLK-To-OUT (Nonpipelined) 15.02 1.08 2.02 4.62 2.24 5.31 3.57 5.48 13.36 6.75 0 0.95 7.51 17.1 1.23 2.3 5.26 2.55 6.05 4.06 6.24 5.78 0.22 0.98 6.68 15.2 7.69 0 1.08 8.55 20.1 1.45 2.7 6.19 3 7.11 4.77 7.34 6.58 0.25 1.11 7.6 17.88 9.04 0 1.27 10.05 7.74 0.3 1.31 8.94 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
Table 2-101 * Sixteen FIFO Blocks Cascaded Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, TJ = 70C '-2' Speed Parameter FIFO Module Timing tWSU tWHD tWCKH tWCKL tWCKP tRSU tRHD tRCKH tRCKL tRCKP tCLRHF tCLR2FF tCLR2AF tCK2FF tCK2AF tRCK2RD1 tRCK2RD2 Write Setup Write Hold WCLK High WCLK Low Minimum WCLK Period Read Setup Read Hold RCLK High RCLK Low Minimum RCLK period Clear High Clear-to-flag (EMPTY/FULL) Clear-to-flag (AEMPTY/AFULL) Clock-to-flag (EMPTY/FULL) Clock-to-flag (AEMPTY/AFULL) RCLK-To-OUT (Pipelined) RCLK-To-OUT (Nonpipelined) 37.5 1.08 2.02 4.62 2.24 5.31 12.71 13.91 34.88 18.13 0 0.95 18.75 42.72 1.23 2.3 5.26 2.55 6.05 14.48 15.85 16.54 0.22 0.98 17.44 39.72 20.65 0 1.08 21.36 50.22 1.45 2.7 6.19 3 7.11 17.03 18.63 18.84 0.25 1.11 19.86 46.7 24.27 0 1.27 25.11 22.15 0.3 1.31 23.35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. '-1' Speed Min. Max. 'Std' Speed Min. Max. Units
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Building RAM and FIFO Modules
RAM and FIFO modules can be generated and included in a design in two different ways: * Using the SmartGen Core Generator where the user defines the depth and width of the FIFO/ RAM, and then instantiates this block into the design (please refer to Actel's SmartGen, FlashROM, Analog System Builder, and Flash Memory System Builder User's Guide for more information). The alternative is to instantiate the RAM/FIFO blocks manually, using inverters for polarity control and tying all unused data bits to ground.
JTAG
Axcelerator offers a JTAG interface that is compliant with the IEEE 1149.1 standard. The user can employ the JTAG interface for probing a design and performing any JTAG Public Instructions as defined in the Table 2-102.
Interface
The interface consists of four inputs: Test Mode Select (TMS), Test Data In (TDI), Test Clock (TCK), TAP Controller Reset (TRST), and an output, Test Data Out (TDO). TMS, TDI, and TRST have on-chip pull-up resistors.
Table 2-102 * JTAG Instruction Code Instruction (IR4:IR0) Extest Preload / Sample Intest USERCODE IDCODE HIGHZ CLAMP Diagnostic Reserved Bypass Binary Code 00000 00001 00010 00011 00100 01110 01111 10000 All others 11111
*
Other Architectural Features
Low Power Mode
Although designed for high performance, the AX architecture also allows the user to place the device into a low power mode. Each I/O bank in an Axcelerator device can be configured individually, when in low power mode, to tristate all outputs, disable inputs, or both. The low power mode is activated by asserting the LP pin, which is grounded in normal operation. While in the low power mode, the device is still fully functional and all internal logic states are preserved. This allows a user to disable all but a few signals and operate the part in a low-frequency, watchdog mode if desired. Please note, if the I/O bank is not disabled, differential I/Os belonging to the I/O bank will still consume normal power, even when operating in the low power mode. The Axcelerator device will resume normal operation 10s after the LP pin is pulled Low. To further reduce power consumption, the internal charge pump can be bypassed and an external power supply voltage can be used instead. This saves the internal charge-pump operating current, resulting in no DC current draw. The Axcelerator family devices have a dedicated "VPUMP" pin that can be used to access an external charge pump device. In normal chip operation, when using the internal charge pump, VPUMP should be tied to GND. When the voltage level on VPUMP is set to 3.3V, the internal charge pump is turned off, and the VPUMP voltage will be used as the charge pump voltage. Adequate voltage regulation (i.e. high drive, low output impedance, and good decoupling) should be used at VPUMP. In addition, any PLL in use can be powered down to further reduce power consumption. This can be done with the PowerDown pin driven Low. Driving this pin High restarts the PLL with the output clock(s) being stable once lock is restored.
TRST
TRST (Test-Logic Reset) is an active-low, asynchronous reset signal to the TAP controller. The TRST input can be used to reset the Test Access Port (TAP) Controller to the TRST state. The TAP Controller can be held at this state permanently by grounding the TRST pin. To hold the JTAG TAP controller in the TRST state, it is recommended to connect TRST to ground via a 1 k resistor. There is an optional internal pull-up resistor available for the TRST input that can be set by the user at programming. Care should be exercised when using this option in combination with an external tie-off to ground. An on-chip power-on-reset (POWRST) circuit is included. POWRST has the same function as "TRST," but it only occurs at power-up or during recovery from a VCCA and/ or VCCDA voltage drop.
TDO
TDO is normally tristated, and it is active only when the TAP controller is in the "Shift_DR" state or "Shift_IR" state. The least significant bit of the selected register (i.e. IR or DR) is clocked out to TDO first by the falling edge of TCK.
TAP Controller
The TAP Controller is compliant with the IEEE Standard 1149.1. It is a state machine of 16 states that controls the
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Instruction Register (IR) and the Data Registers (such as BSR, IDCODE, USRCODE, BYPASS, etc.). The TAP Controller steps into one of the states depending on the sequence of TMS at the rising edges of TCK.
Probing
Internal activities of the JTAG interface can be observed via the Silicon Explorer II probes: "PRA," "PRB," "PRC," and "PRD."
Instruction Register (IR)
The IR has five bits (IR4 to IR0). At the TRST state, IR is reset to IDCODE. Each time when IR is selected, it goes through "select IR-Scan," "Capture-IR," "Shift-IR," all the way through "Update-IR." When there is no test error, the first five data bits coming out of TDO during the "Shift-IR" will be "10111." If a test error occurs, the last three bits will contain one to three zeroes corresponding to negatively asserted signals: "TDO_ERRORB," "PROBA_ERRORB," and "PROBB_ERRORB." The error(s) will be erased when the TAP is at the "Update-IR" or the TRST state. When in user mode start-up sequence, if the micro-probe has not been used, the "PROBA_ERRORB" is used as a "Power-up done successfully" flag.
Special Fuses
Security
Actel antifuse FPGAs, with FuseLock technology, offer the highest level of design security available in a programmable logic device. Since antifuse FPGAs are live-at power-up, there is no bitstream that can be intercepted, and no bitstream or programming data is ever downloaded to the device during power-up, thus making device cloning impossible. In addition, special security fuses are hidden throughout the fabric of the device and may be programmed by the user to thwart attempts to reverse engineer the device by attempting to exploit either the programming or probing interfaces. Both invasive and noninvasive attacks against an Axcelerator device that access or bypass these security fuses will destroy access to the rest of the device. (refer to the Design Security in Nonvolatile Flash and Antifuse FPGAs white paper). Look for this symbol to ensure your valuable IP is secure.
Data Registers (DRs)
Data registers are distributed throughout the chip. They store testing/programming vectors. The MSB of a data register is connected to TDI, while the LSB is connected to TDO. There are different types of data registers. Descriptions of the main registers are as follow: 1. IDCODE: The IDCODE is a 33-bit hard coded JTAG Silicon Signature. It is a hardwired device ID code, which contains the Actel identity, part number, and version number in a specific JTAG format. 2. USERCODE: The USERCODE is a 32-bit programmable JTAG Silicon Signature. It is a supplementary identity code for the user to program information to distinguish different programmed parts. USERCODE fuses will read out as "zeroes" when not programmed, so only the "1" bits need to be programmed. 3. Boundary-Scan Register (BSR): Each I/O contains three Boundary-Scan Cells. Each cell has a shift register bit, a latch, and two MUXes. The boundary-scan cells are used for the Output-enable (E), Output (O), and Input (I) registers. The bit order of the boundary-scan cells for each of them is E-O-I. The boundary-scan cells are then chained serially to form the Boundary-Scan Register (BSR). The length of the BSR is the number of I/Os in the die multiplied by three. 4. Bypass Register (BYR): This is the "1-bit" register. It is used to shorten the TDI-TDO serial chain in board-level testing to only one bit per device not being tested. It is also selected for all "reserved" or unused instructions.
TM
ue
Figure 2-69 * FuseLock Logo
To ensure maximum security in Axcelerator devices, it is recommended that the user program the device security fuse (SFUS). When programmed, the Silicon Explorer II testing probes are disabled to prevent internal probing, and the programming interface is also disabled. All JTAG public instructions are still accessible by the user. For more information, refer to Actel's Implementation of Security in Actel Antifuse FPGAs application note.
Global Set Fuse
The Global Set Fuse determines if all R-cells and I/O registers (InReg, OutReg, and EnReg) are either cleared or preset by driving the GCLR and GPSET inputs of all Rcells and I/O Registers (Figure 2-31 on page 2-47). Default setting is to clear all registers (GCLR = 0 and GPSET =1) at device power-up. When the GBSETFUS option is checked during FUSE file generation, all registers are preset (GCLR = 1 and GPSET= 0). A local CLR or PRESET will take precedence over this setting. Both pins are pulled High during normal device operation. For use details, see the Libero IDE online help.
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Silicon Explorer II Probe Interface
Silicon Explorer II is an integrated hardware and software solution that, in conjunction with the Designer tools, allows users to examine any of the internal nets (except I/O registers) of the device while it is operating in a prototype or a production system. The user can probe up to four nodes at a time without changing the placement and routing of the design and without using any additional device resources. Highlighted nets in Designer's ChipPlanner can be accessed using Silicon Explorer II in order to observe their real time values. Silicon Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle. In addition, Silicon Explorer II does not require relayout or additional MUXes to bring signals out to external pins, which is necessary when using programmable logic devices from other suppliers. By eliminating multiple place-and-route program cycles, the integrity of the design is maintained throughout the debug process. Each member of the Axcelerator family has four external pads: PRA, PRB, PRC, and PRD. These can be used to bring out four probe signals from the Axcelerator device (note that the AX125 only has two probe signals that can be observed: PRA and PRB). Each core tile has up to two probe signals. To disallow probing, the SFUS security fuse in the silicon signature has to be programmed (see "Special Fuses" on page 2-90). Silicon Explorer II connects to the host PC using a standard serial port connector. Connections to the circuit board are achieved using a nine-pin D-Sub connector (Figure 1-9 on page 1-7). Once the design has been placed-and-routed, and the Axcelerator device has been programmed, Silicon Explorer II can be connected and the Explorer software can be launched. Silicon Explorer II comes with an additional optional PC hosted tool that emulates an 18-channel logic analyzer. Four channels are used to monitor four internal nodes, and 14 channels are available to probe external signals. The software included with the tool provides the user with an intuitive interface that allows for easy viewing and editing of signal waveforms.
Programming
Device programming is supported through the Silicon Sculptor II, a single-site, robust and compact device programmer for the PC. Up to four Silicon Sculptor IIs can be daisy-chained and controlled from a single PC host. With standalone software for the PC, Silicon Sculptor II is designed to allow concurrent programming of multiple units from the same PC when daisy-chained. Silicon Sculptor II programs devices independently to achieve the fastest programming times possible. Each fuse is verified by Silicon Sculptor II to ensure correct programming. Furthermore, at the end of programming, there are integrity tests that are run to ensure that programming was completed properly. Not only does it test programmed and nonprogrammed fuses, Silicon Sculptor II also provides a self-test to test its own hardware extensively. Programming an Axcelerator device using Silicon Sculptor II is similar to programming any other antifuse device. The procedure is as follows: 1. Load the .AFM file. 2. Select the device to be programmed. 3. Begin programming. When the design is ready to go to production, Actel offers device volume-programming services either through distribution partners or via our In-House Programming Center. In addition, BP programmers that Axcelerator devices. Microsystems offers multi-site provide qualified support for
For more details on programming the Axcelerator devices, please refer to the Silicon Sculptor II User's Guide.
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Package Pin Assignments
180-Pin CSP
A1 Ball Pad Corner 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P
Figure 3-1 * 180-Pin CSP (Bottom View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
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180-Pin CSP AX125 Function Bank 0 IO00NB0F0 IO00PB0F0 IO02NB0F0 IO02PB0F0 IO07NB0F0/HCLKAN IO07PB0F0/HCLKAP IO08NB0F0/HCLKBN IO08PB0F0/HCLKBP Bank 1 IO09NB1F1/HCLKCN IO09PB1F1/HCLKCP IO10NB1F1/HCLKDN IO10PB1F1/HCLKDP IO11NB1F1 IO11PB1F1 IO15NB1F1 IO15PB1F1 IO17NB1F1 IO17PB1F1 Bank 2 IO18NB2F2 IO18PB2F2 IO19NB2F2 IO19PB2F2 IO20NB2F2 IO20PB2F2 IO22NB2F2 IO22PB2F2 IO24NB2F2 IO24PB2F2 IO26NB2F2 IO26PB2F2 IO28NB2F2 IO28PB2F2 Bank 3 IO30NB3F3 IO30PB3F3 H13 G13 C13 C12 C14 B14 D13 D14 F12 E12 E13 E14 F13 F14 G12 G11 C9 C8 A10 B10 B11 A11 B12 A12 D12 D11 B3 A3 B4 A4 B5 A5 B7 B6 Pin Number
180-Pin CSP AX125 Function IO32NB3F3 IO32PB3F3 IO34NB3F3 IO34PB3F3 IO36NB3F3 IO36PB3F3 IO38NB3F3 IO38PB3F3 IO40NB3F3 IO40PB3F3 IO41NB3F3 IO41PB3F3 Bank 4 IO42NB4F4 IO42PB4F4 IO43NB4F4 IO43PB4F4 IO46NB4F4 IO46PB4F4 IO47NB4F4 IO47PB4F4 IO49NB4F4/CLKEN IO49PB4F4/CLKEP IO50NB4F4/CLKFN IO50PB4F4/CLKFP Bank 5 IO51NB5F5/CLKGN IO51PB5F5/CLKGP IO52NB5F5/CLKHN IO52PB5F5/CLKHP IO53NB5F5 IO53PB5F5 IO55NB5F5 IO55PB5F5 IO56NB5F5 IO56PB5F5 IO57NB5F5 IO57PB5F5 M7 M8 P5 N5 P4 N4 P3 N3 M4 M5 M2 M3 P13 N13 L12 M12 P12 N12 N11 P11 M11 M10 N9 P9 Pin Number H11 H12 K14 J14 K13 J13 L13 L14 M13 M14 K12 J12
180-Pin CSP AX125 Function IO59NB5F5 IO59PB5F5 Bank 6 IO60NB6F6 IO60PB6F6 IO62NB6F6 IO62PB6F6 IO64NB6F6 IO64PB6F6 IO66NB6F6 IO66PB6F6 IO68NB6F6 IO68PB6F6 IO70NB6F6 IO70PB6F6 IO71NB6F6 IO71PB6F6 Bank 7 IO72NB7F7 IO72PB7F7 IO74NB7F7 IO74PB7F7 IO76NB7F7 IO76PB7F7 IO78NB7F7 IO78PB7F7 IO79NB7F7 IO79PB7F7 IO83NB7F7 IO83PB7F7 Dedicated I/O VCCDA GND GND GND GND GND GND B1 A1 A14 A7 A8 E10 E5 G2 H2 F3 G3 F1 F2 E1 E2 D2 D1 C1 C2 M1 N1 K3 L3 L2 L1 K2 K1 H3 J3 G4 H4 J1 J2 Pin Number N2 P2
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180-Pin CSP AX125 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND/LP PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE Pin Number E6 E9 F10 F5 G1 G14 H1 H14 J10 J5 K10 K5 K6 K9 N14 P1 P14 P7 P8 C3 D8 B8 N8 N7 C4 E3 C5 D4 B2 E7 G10 H5 K8 C6 C7 A9 C10 N10
180-Pin CSP AX125 Function VCCPLF VCCPLG VCCPLH VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCDA VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number L8 P6 M6 B13 D3 E8 G5 H10 K7 L11 L4 D5 D6 D10 D9 E11 F11 J11 K11 L10 L9 L5 L6 J4 K4 E4 F4 A2 A6 D7 B9 C11 P10 M9 N6 L7 A13
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729-Pin PBGA
A1 Ball Pad Corner 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG
Figure 3-2 * 729-Pin PBGA (Bottom View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
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729-Pin PBGA AX1000 Function Bank 0 IO00NB0F0 IO00PB0F0 IO01NB0F0 IO01PB0F0 IO02NB0F0 IO02PB0F0 IO03NB0F0 IO03PB0F0 IO04NB0F0 IO04PB0F0 IO05NB0F0 IO05PB0F0 IO06NB0F0 IO06PB0F0 IO07NB0F0 IO07PB0F0 IO08NB0F0 IO08PB0F0 IO09NB0F0 IO09PB0F0 IO10NB0F0 IO10PB0F0 IO11NB0F0 IO11PB0F0 IO12NB0F1 IO12PB0F1 IO13NB0F1 IO13PB0F1 IO14NB0F1 IO14PB0F1 IO15NB0F1 IO15PB0F1 IO16NB0F1 IO16PB0F1 IO17NB0F1 IO17PB0F1 IO18NB0F1 E6 F6 G8 G7 D7 E7 D5 E5 G9 H9 E8 F8 C6 D6 B5 C5 A6 A5 E9 F9 G10 H10 B7 B6 C8 C7 E10 F10 G11 H11 D9 D8 A8 A7 B9 B8 C10 Pin Number
729-Pin PBGA AX1000 Function IO18PB0F1 IO19NB0F1 IO19PB0F1 IO20NB0F1 IO20PB0F1 IO21NB0F1 IO21PB0F1 IO22NB0F2 IO22PB0F2 IO23NB0F2 IO23PB0F2 IO24NB0F2 IO24PB0F2 IO25NB0F2 IO25PB0F2 IO26NB0F2 IO26PB0F2 IO27NB0F2 IO27PB0F2 IO28NB0F2 IO28PB0F2 IO29NB0F2 IO29PB0F2 IO30NB0F2/HCLKAN IO30PB0F2/HCLKAP IO31NB0F2/HCLKBN IO31PB0F2/HCLKBP Bank 1 IO32NB1F3/HCLKCN IO32PB1F3/HCLKCP IO33NB1F3/HCLKDN IO33PB1F3/HCLKDP IO34NB1F3 IO34PB1F3 IO35NB1F3 IO35PB1F3 IO36NB1F3 IO36PB1F3 C14 B14 D16 D15 B16 A16 E15 F15 H15 G15 Pin Number C9 E11 F11 G12 H12 D11 D10 A10 A9 B11 B10 G13 H13 C12 C11 E12 D12 E13 F13 G14 H14 A12 B12 C13 D13 F14 E14
729-Pin PBGA AX1000 Function IO37NB1F3 IO37PB1F3 IO38NB1F3 IO38PB1F3 IO39NB1F3 IO39PB1F3 IO40NB1F3 IO40PB1F3 IO41NB1F4 IO41PB1F4 IO42NB1F4 IO42PB1F4 IO43NB1F4 IO43PB1F4 IO44NB1F4 IO44PB1F4 IO45NB1F4 IO45PB1F4 IO46NB1F4 IO46PB1F4 IO47NB1F4 IO47PB1F4 IO48NB1F4 IO48PB1F4 IO49NB1F4 IO49PB1F4 IO50NB1F4 IO50PB1F4 IO51NB1F4 IO51PB1F4 IO52NB1F4 IO52PB1F4 IO53NB1F4 IO53PB1F4 IO54NB1F5 IO54PB1F5 IO55NB1F5 IO55PB1F5 Pin Number C17 C16 B18 B17 A18 A17 H16 G16 B19 A19 C19 C18 D18 D17 H17 G17 F17 E17 B20 A20 C21 C20 H18 G18 F18 E18 D20 D19 A22 A21 B22 B21 F19 E19 F20 E20 E21 D21
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Axcelerator Family FPGAs
729-Pin PBGA AX1000 Function IO56NB1F5 IO56PB1F5 IO57NB1F5 IO57PB1F5 IO58NB1F5 IO58PB1F5 IO59NB1F5 IO59PB1F5 IO60NB1F5 IO60PB1F5 IO61NB1F5 IO61PB1F5 IO62NB1F5 IO62PB1F5 IO63NB1F5 IO63PB1F5 Bank 2 IO64NB2F6 IO64PB2F6 IO65NB2F6 IO65PB2F6 IO66NB2F6 IO66PB2F6 IO67NB2F6 IO67PB2F6 IO68NB2F6 IO68PB2F6 IO69NB2F6 IO69PB2F6 IO70NB2F6 IO70PB2F6 IO71NB2F6 IO71PB2F6 IO72NB2F6 IO72PB2F6 IO73NB2F6 IO73PB2F6 IO74NB2F7 J21 H21 F24 F23 F26 F25 E26 E25 J22 H22 G24 G23 K20 J20 G26 G25 J24 J23 H24 H23 L21 Pin Number H19 G19 D22 C22 B23 A23 D23 C23 G21 G20 E23 E22 F22 F21 H20 J19
729-Pin PBGA AX1000 Function IO74PB2F7 IO75NB2F7 IO75PB2F7 IO76NB2F7 IO76PB2F7 IO77NB2F7 IO77PB2F7 IO78NB2F7 IO78PB2F7 IO79NB2F7 IO79PB2F7 IO80NB2F7 IO80PB2F7 IO81NB2F7 IO81PB2F7 IO82NB2F7 IO82PB2F7 IO83NB2F7 IO83PB2F7 IO84NB2F7 IO84PB2F7 IO85NB2F8 IO85PB2F8 IO86NB2F8 IO86PB2F8 IO87NB2F8 IO87PB2F8 IO88NB2F8 IO88PB2F8 IO89NB2F8 IO89PB2F8 IO90NB2F8 IO90PB2F8 IO91NB2F8 IO91PB2F8 IO92NB2F8 IO92PB2F8 IO93NB2F8 Pin Number K21 G27 F27 K23 K22 H26 H25 K25 K24 J26 J25 M20 L20 J27 H27 L23 L22 L25 L24 N21 M21 K27 K26 M23 M22 M25 M24 L27 L26 M27 M26 N23 N22 N25 N24 N27 N26 P26
729-Pin PBGA AX1000 Function IO93PB2F8 IO94NB2F8 IO94PB2F8 IO95NB2F8 IO95PB2F8 Bank 3 IO96NB3F9 IO96PB3F9 IO97NB3F9 IO97PB3F9 IO98NB3F9 IO98PB3F9 IO99NB3F9 IO99PB3F9 IO100NB3F9 IO100PB3F9 IO101NB3F9 IO101PB3F9 IO102NB3F9 IO102PB3F9 IO103NB3F9 IO103PB3F9 IO104NB3F9 IO104PB3F9 IO105NB3F9 IO105PB3F9 IO106NB3F9 IO106PB3F9 IO107NB3F10 IO107PB3F10 IO108NB3F10 IO108PB3F10 IO109NB3F10 IO109PB3F10 IO110NB3F10 IO110PB3F10 IO111NB3F10 IO111PB3F10 P25 P24 R26 R27 P21 P20 R24 R25 T26 T27 T24 T25 R20 R21 R23 R22 U26 U27 U24 U25 R19 P19 V26 V27 T23 T22 V24 V25 T20 T21 W26 W27 Pin Number P27 N19 N20 P23 P22
3 -6
v2.7
Axcelerator Family FPGAs
729-Pin PBGA AX1000 Function IO112NB3F10 IO112PB3F10 IO113NB3F10 IO113PB3F10 IO114NB3F10 IO114PB3F10 IO115NB3F10 IO115PB3F10 IO116NB3F10 IO116PB3F10 IO117NB3F10 IO117PB3F10 IO118NB3F11 IO118PB3F11 IO119NB3F11 IO119PB3F11 IO120NB3F11 IO120PB3F11 IO121NB3F11 IO121PB3F11 IO122NB3F11 IO122PB3F11 IO123NB3F11 IO123PB3F11 IO124NB3F11 IO124PB3F11 IO125NB3F11 IO125PB3F11 IO126NB3F11 IO126PB3F11 IO127NB3F11 IO127PB3F11 IO128NB3F11 IO128PB3F11 Bank 4 IO129NB4F12 IO129PB4F12 IO130NB4F12 AA20 Y21 AB22 Pin Number U22 U23 Y26 Y27 U20 U21 W24 W25 V22 V23 Y24 Y25 V20 V21 AA26 AA27 W22 W23 AA24 AA25 W20 W21 AB26 AB27 Y22 Y23 AB24 AB25 AA22 AA23 AC26 AC27 Y20 W19
729-Pin PBGA AX1000 Function IO130PB4F12 IO131NB4F12 IO131PB4F12 IO132NB4F12 IO132PB4F12 IO133NB4F12 IO133PB4F12 IO134NB4F12 IO134PB4F12 IO135NB4F12 IO135PB4F12 IO136NB4F12 IO136PB4F12 IO137NB4F12 IO137PB4F12 IO138NB4F12 IO138PB4F12 IO139NB4F13 IO139PB4F13 IO140NB4F13 IO140PB4F13 IO141NB4F13 IO141PB4F13 IO142NB4F13 IO142PB4F13 IO143NB4F13 IO143PB4F13 IO144NB4F13 IO144PB4F13 IO145NB4F13 IO145PB4F13 IO146NB4F13 IO146PB4F13 IO147NB4F13 IO147PB4F13 IO148NB4F13 IO148PB4F13 IO149NB4F13 Pin Number AB23 AC22 AC23 AD23 AD24 AF23 AE23 AC21 AB21 AC20 AB20 AD21 AD22 Y19 AA19 AE21 AE22 AF21 AF22 AG22 AG23 Y18 AA18 AE20 AD20 AG20 AG21 AC19 AB19 AD18 AD19 AC18 AB18 Y17 AA17 AF19 AF20 AC17
729-Pin PBGA AX1000 Function IO149PB4F13 IO150NB4F13 IO150PB4F13 IO151NB4F13 IO151PB4F13 IO152NB4F14 IO152PB4F14 IO153NB4F14 IO153PB4F14 IO154NB4F14 IO154PB4F14 IO155NB4F14 IO155PB4F14 IO156NB4F14 IO156PB4F14 IO157NB4F14 IO157PB4F14 IO158NB4F14 IO158PB4F14 IO159NB4F14/CLKEN IO159PB4F14/CLKEP IO160NB4F14/CLKFN IO160PB4F14/CLKFP Bank 5 IO161NB5F15/CLKGN IO161PB5F15/CLKGP IO162NB5F15/CLKHN IO162PB5F15/CLKHP IO163NB5F15 IO163PB5F15 IO164NB5F15 IO164PB5F15 IO165NB5F15 IO165PB5F15 IO166NB5F15 IO166PB5F15 IO167NB5F15 IO167PB5F15 AE14 AE15 AC13 AD13 Y14 AA14 AE13 AF13 AF12 AG12 AD12 AE12 Y13 AA13 Pin Number AB17 AE18 AE19 AA16 Y16 AG18 AG19 AC16 AB16 AF17 AF18 AB15 AC15 AE16 AE17 Y15 AA15 AG16 AG17 AF15 AF16 AD14 AD15
v2.7
3-7
Axcelerator Family FPGAs
729-Pin PBGA AX1000 Function IO168NB5F15 IO168PB5F15 IO169NB5F15 IO169PB5F15 IO170NB5F15 IO170PB5F15 IO171NB5F16 IO171PB5F16 IO172NB5F16 IO172PB5F16 IO173NB5F16 IO173PB5F16 IO174NB5F16 IO174PB5F16 IO175NB5F16 IO175PB5F16 IO176NB5F16 IO176PB5F16 IO177NB5F16 IO177PB5F16 IO178NB5F16 IO178PB5F16 IO179NB5F16 IO179PB5F16 IO180NB5F16 IO180PB5F16 IO181NB5F17 IO181PB5F17 IO182NB5F17 IO182PB5F17 IO183NB5F17 IO183PB5F17 IO184NB5F17 IO184PB5F17 IO185NB5F17 IO185PB5F17 IO186NB5F17 IO186PB5F17 Pin Number AD11 AE11 AG11 AF11 AB11 AC11 AF10 AG10 AD10 AE10 Y12 AA12 AB10 AC10 AF9 AG9 AD9 AE9 Y11 AA11 AF8 AG8 AD8 AE8 AB9 AC9 Y10 AA10 AF7 AG7 AD7 AE7 AC7 AC8 AF6 AG6 AB7 AB8
729-Pin PBGA AX1000 Function IO187NB5F17 IO187PB5F17 IO188NB5F17 IO188PB5F17 IO189NB5F17 IO189PB5F17 IO190NB5F17 IO190PB5F17 IO191NB5F17 IO191PB5F17 IO192NB5F17 IO192PB5F17 Bank 6 IO193NB6F18 IO193PB6F18 IO194NB6F18 IO194PB6F18 IO195NB6F18 IO195PB6F18 IO196NB6F18 IO196PB6F18 IO197NB6F18 IO197PB6F18 IO198NB6F18 IO198PB6F18 IO199NB6F18 IO199PB6F18 IO200NB6F18 IO200PB6F18 IO201NB6F18 IO201PB6F18 IO202NB6F18 IO202PB6F18 IO203NB6F19 IO203PB6F19 IO204NB6F19 IO204PB6F19 IO205NB6F19 W8 Y7 AB5 AC5 AC2 AC3 AC4 AD4 Y5 Y6 AB3 AB4 V7 W7 AA4 AA5 W5 W6 AB1 AC1 Y3 AA3 AA2 AB2 U8 Pin Number Y9 AA9 AD6 AE6 AB6 AC6 AF5 AG5 AA6 AA7 Y8 AA8
729-Pin PBGA AX1000 Function IO205PB6F19 IO206NB6F19 IO206PB6F19 IO207NB6F19 IO207PB6F19 IO208NB6F19 IO208PB6F19 IO209NB6F19 IO209PB6F19 IO210NB6F19 IO210PB6F19 IO211NB6F19 IO211PB6F19 IO212NB6F19 IO212PB6F19 IO213NB6F19 IO213PB6F19 IO214NB6F20 IO214PB6F20 IO215NB6F20 IO215PB6F20 IO216NB6F20 IO216PB6F20 IO217NB6F20 IO217PB6F20 IO218NB6F20 IO218PB6F20 IO219NB6F20 IO219PB6F20 IO220NB6F20 IO220PB6F20 IO221NB6F20 IO221PB6F20 IO222NB6F20 IO222PB6F20 IO223NB6F20 IO223PB6F20 IO224NB6F20 Pin Number V8 V5 V6 Y1 AA1 W4 Y4 T7 U7 W2 Y2 U5 U6 V3 W3 R9 T8 U4 V4 T5 T6 V1 W1 R7 R8 U2 V2 T1 U1 R5 R6 T3 T4 R2 T2 P8 P9 R3
3 -8
v2.7
Axcelerator Family FPGAs
729-Pin PBGA AX1000 Function IO224PB6F20 Bank 7 IO225NB7F21 IO225PB7F21 IO226NB7F21 IO226PB7F21 IO227NB7F21 IO227PB7F21 IO228NB7F21 IO228PB7F21 IO229NB7F21 IO229PB7F21 IO230NB7F21 IO230PB7F21 IO231NB7F21 IO231PB7F21 IO232NB7F21 IO232PB7F21 IO233NB7F21 IO233PB7F21 IO234NB7F21 IO234PB7F21 IO235NB7F21 IO235PB7F21 IO236NB7F22 IO236PB7F22 IO237NB7F22 IO237PB7F22 IO238NB7F22 IO238PB7F22 IO239NB7F22 IO239PB7F22 IO240NB7F22 IO240PB7F22 IO241NB7F22 IO241PB7F22 IO242NB7F22 IO242PB7F22 P1 R1 P3 P2 N7 P7 P5 P4 N2 N1 N6 P6 N9 N8 N4 N3 M2 M1 M4 M3 M5 N5 L2 L1 L4 L3 L6 M6 M8 M7 K2 K1 K4 K3 K5 L5 Pin Number R4
729-Pin PBGA AX1000 Function IO243NB7F22 IO243PB7F22 IO244NB7F22 IO244PB7F22 IO245NB7F22 IO245PB7F22 IO246NB7F22 IO246PB7F22 IO247NB7F23 IO247PB7F23 IO248NB7F23 IO248PB7F23 IO249NB7F23 IO249PB7F23 IO250NB7F23 IO250PB7F23 IO251NB7F23 IO251PB7F23 IO252NB7F23 IO252PB7F23 IO253NB7F23 IO253PB7F23 IO254NB7F23 IO254PB7F23 IO255NB7F23 IO255PB7F23 IO256NB7F23 IO256PB7F23 IO257NB7F23 IO257PB7F23 Dedicated I/O GND GND GND GND GND GND GND A1 A2 A25 A26 A27 A3 AC24 Pin Number J2 J1 J4 J3 H2 H1 H4 H3 L8 L7 J6 K6 H5 J5 G2 G1 K8 K7 G4 G3 F2 F1 G6 H6 F5 G5 F3 F4 H7 J7
729-Pin PBGA AX1000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AE1 AE2 AE25 AE26 AE27 AE3 AE5 AF1 AF2 AF25 AF26 AF27 AF3 AG1 AG2 AG25 AG26 AG27 AG3 B1 B2 B25 B26 B27 B3 C1 C2 C25 C26 C27 C3 E27 L11 L12 L13 L14 L15 L16
v2.7
3-9
Axcelerator Family FPGAs
729-Pin PBGA AX1000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number L17 M11 M12 M13 M14 M15 M16 M17 N11 N12 N13 N14 N15 N16 N17 P11 P12 P13 P14 P15 P16 P17 R11 R12 R13 R14 R15 R16 R17 T11 T12 T13 T14 T15 T16 T17 U11 U12
729-Pin PBGA AX1000 Function GND GND GND GND GND GND/LP NC PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF Pin Number U13 U14 U15 U16 U17 J8 U3 J14 D14 V14 AB14 E4 D4 J9 H8 E3 AA21 AD5 E1 G22 K10 K11 K17 K18 L10 L18 U10 U18 V10 V11 V17 V18 A13 J13 B15 C15 AG14 AF14
729-Pin PBGA AX1000 Function VCCPLG VCCPLH VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 Pin Number AB13 AG13 A11 AB12 AC12 AC25 AD16 AD17 E16 E2 E24 F12 F16 F7 K14 P10 P18 W14 W9 A4 B4 C4 J10 J11 J12 K12 K13 A24 B24 C24 J16 J17 J18 K15 K16 D25 D26 D27
3 -1 0
v2.7
Axcelerator Family FPGAs
729-Pin PBGA AX1000 Function VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 Pin Number K19 L19 M18 M19 N18 AD25 AD26 AD27 R18 T18 T19 U19 V19 AE24 AF24 AG24 V15 V16 W16 W17 W18 AE4 AF4 AG4 V12 V13 W10 W11 W12 AD1 AD2 AD3 R10 T10 T9 U9 V9 D1
729-Pin PBGA AX1000 Function VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number D2 D3 K9 L9 M10 M9 N10 B13 A14 A15 J15 AG15 W15 AC14 W13 D24
v2.7
3-11
Axcelerator Family FPGAs
256-Pin FBGA
A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T
Figure 3-3 * 256-Pin FBGA (Bottom View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
3 -1 2
v2.7
Axcelerator Family FPGAs
256-Pin FBGA AX125 Function Bank 0 IO01NB0F0 IO01PB0F0 IO03NB0F0 IO03PB0F0 IO04NB0F0 IO04PB0F0 IO06NB0F0 IO06PB0F0 IO07NB0F0/HCLKAN IO07PB0F0/HCLKAP IO08NB0F0/HCLKBN IO08PB0F0/HCLKBP Bank 1 IO09NB1F1/HCLKCN IO09PB1F1/HCLKCP IO10NB1F1/HCLKDN IO10PB1F1/HCLKDP IO12NB1F1 IO12PB1F1 IO13NB1F1 IO13PB1F1 IO14NB1F1 IO14PB1F1 IO15NB1F1 IO15PB1F1 IO16NB1F1 IO16PB1F1 IO17NB1F1 IO17PB1F1 Bank 2 IO18NB2F2 IO18PB2F2 IO19NB2F2 IO19PB2F2 IO20NB2F2 IO20PB2F2 IO21NB2F2 F13 E13 F14 E14 F15 E15 C16 C10 C9 B11 B10 A13 A12 B13 B12 C12 C11 A15 B14 C15 C14 D13 D12 B4 B3 A4 A3 B6 B5 A6 A5 B8 B7 A9 A8 Pin Number
256-Pin FBGA AX125 Function IO21PB2F2 IO22NB2F2 IO22PB2F2 IO23NB2F2 IO23PB2F2 IO25NB2F2 IO25PB2F2 IO26NB2F2 IO26PB2F2 IO27NB2F2 IO27PB2F2 IO28NB2F2 IO28PB2F2 IO29NB2F2 IO29PB2F2 Bank 3 IO30NB3F3 IO30PB3F3 IO31NB3F3 IO31PB3F3 IO33NB3F3 IO33PB3F3 IO35NB3F3 IO35PB3F3 IO36PB3F3 IO37NB3F3 IO37PB3F3 IO39NB3F3 IO39PB3F3 IO40NB3F3 IO40PB3F3 IO41NB3F3 IO41PB3F3 Bank 4 IO42NB4F4 IO42PB4F4 IO43NB4F4 IO43PB4F4 N12 N13 T14 R14 K13 J13 K14 J14 L15 L16 P16 N16 M16 P15 R16 N15 M15 M13 L13 M14 L14 Pin Number B16 H13 G13 E16 D16 H15 G15 H14 G14 G16 F16 K15 K16 J16 H16
256-Pin FBGA AX125 Function IO44PB4F4 IO45NB4F4 IO45PB4F4 IO46NB4F4 IO46PB4F4 IO47PB4F4 IO48NB4F4 IO48PB4F4 IO49NB4F4/CLKEN IO49PB4F4/CLKEP IO50NB4F4/CLKFN IO50PB4F4/CLKFP Bank 5 IO51NB5F5/CLKGN IO51PB5F5/CLKGP IO52NB5F5/CLKHN IO52PB5F5/CLKHP IO54NB5F5 IO54PB5F5 IO55NB5F5 IO55PB5F5 IO56NB5F5 IO56PB5F5 IO57NB5F5 IO57PB5F5 IO58NB5F5 IO58PB5F5 IO59NB5F5 IO59PB5F5 Bank 6 IO60NB6F6 IO60PB6F6 IO61NB6F6 IO61PB6F6 IO63NB6F6 IO63PB6F6 IO64NB6F6 IO64PB6F6 L4 M4 L3 M3 P2 N2 J4 K4 P7 P8 R6 R7 T5 T6 P5 P6 T3 T4 R3 R4 R1 T2 N4 N5 Pin Number T15 R12 R13 P11 P12 T11 T12 T13 R9 R10 T8 T9
v2.7
3-13
Axcelerator Family FPGAs
256-Pin FBGA AX125 Function IO65NB6F6 IO65PB6F6 IO67NB6F6 IO67PB6F6 IO69NB6F6 IO69PB6F6 IO70NB6F6 IO70PB6F6 IO71NB6F6 IO71PB6F6 Bank 7 IO72NB7F7 IO72PB7F7 IO73NB7F7 IO73PB7F7 IO74NB7F7 IO74PB7F7 IO75NB7F7 IO75PB7F7 IO76NB7F7 IO77NB7F7 IO77PB7F7 IO78NB7F7 IO78PB7F7 IO79NB7F7 IO79PB7F7 IO81NB7F7 IO81PB7F7 IO82NB7F7 IO82PB7F7 IO83NB7F7 IO83PB7F7 Dedicated I/O VCCDA GND GND GND GND E4 A1 A16 B15 B2 J1 K1 G2 H2 G3 H3 E1 F1 G1 E2 F2 G4 H4 C1 D1 C2 B1 D2 D3 E3 F3 Pin Number N1 P1 L2 M2 L1 M1 J3 K3 J2 K2
256-Pin FBGA AX125 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND/LP NC NC NC PRA PRB PRC Pin Number D15 E12 E5 F11 F6 G10 G7 G8 G9 H10 H7 H8 H9 J10 J7 J8 J9 K10 K7 K8 K9 L11 L6 M12 M5 P13 P3 R15 R2 T1 T16 D4 A11 R11 R5 D8 C8 N9
256-Pin FBGA AX125 Function PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCCDA VCCDA VCCDA VCCDA Pin Number P9 D5 C6 C4 C3 C5 D14 F10 F4 F7 F8 F9 G11 G6 H11 H6 J11 J6 K11 K6 L10 L7 L8 L9 N3 P14 C7 D6 A10 D10 P10 N11 T7 N7 A2 C13 D9 H1
3 -1 4
v2.7
Axcelerator Family FPGAs
256-Pin FBGA AX125 Function VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number J15 N14 N8 P4 E6 E7 E8 E10 E11 E9 F12 G12 H12 J12 K12 L12 M10 M11 M9 M6 M7 M8 J5 K5 L5 F5 G5 H5 A7 D7 B9 D11 T10 N10 R8 N6 A14
256-Pin FBGA AX250 Function Bank 0 IO01NB0F0 IO01PB0F0 IO03NB0F0 IO03PB0F0 IO05NB0F0 IO05PB0F0 IO07NB0F0 IO07PB0F0 IO12NB0F0/HCLKAN IO12PB0F0/HCLKAP IO13NB0F0/HCLKBN IO13PB0F0/HCLKBP Bank 1 IO14NB1F1/HCLKCN IO14PB1F1/HCLKCP IO15NB1F1/HCLKDN IO15PB1F1/HCLKDP IO17NB1F1 IO17PB1F1 IO19NB1F1 IO19PB1F1 IO21NB1F1 IO21PB1F1 IO23NB1F1 IO23PB1F1 IO26NB1F1 IO26PB1F1 IO27NB1F1 IO27PB1F1 Bank 2 IO29NB2F2 IO29PB2F2 IO30NB2F2 IO30PB2F2 IO32NB2F2 IO32PB2F2 IO33NB2F2 F13 E13 F14 E14 C16 B16 F15 C10 C9 B11 B10 A13 A12 B13 B12 C12 C11 A15 B14 C15 C14 D13 D12 B4 B3 A4 A3 B6 B5 A6 A5 B8 B7 A9 A8 Pin Number
256-Pin FBGA AX250 Function IO33PB2F2 IO35NB2F2 IO35PB2F2 IO36NB2F2 IO36PB2F2 IO38NB2F2 IO38PB2F2 IO39NB2F2 IO39PB2F2 IO40NB2F2 IO40PB2F2 IO43NB2F2 IO43PB2F2 IO44NB2F2 IO44PB2F2 Bank 3 IO45NB3F3 IO45PB3F3 IO46NB3F3 IO46PB3F3 IO52NB3F3 IO52PB3F3 IO54NB3F3 IO54PB3F3 IO55PB3F3 IO56NB3F3 IO56PB3F3 IO58NB3F3 IO58PB3F3 IO59NB3F3 IO59PB3F3 IO61NB3F3 IO61PB3F3 Bank 4 IO62NB4F4 IO62PB4F4 IO63NB4F4 IO63PB4F4 N12 N13 T14 R14 K13 J13 K14 J14 L15 L16 P16 N16 M16 P15 R16 N15 M15 M13 L13 M14 L14 Pin Number E15 H13 G13 E16 D16 H15 G15 H14 G14 G16 F16 K15 K16 J16 H16
v2.7
3-15
Axcelerator Family FPGAs
256-Pin FBGA AX250 Function IO66PB4F4 IO67NB4F4 IO67PB4F4 IO69NB4F4 IO69PB4F4 IO70PB4F4 IO73NB4F4 IO73PB4F4 IO74NB4F4/CLKEN IO74PB4F4/CLKEP IO75NB4F4/CLKFN IO75PB4F4/CLKFP Bank 5 IO76NB5F5/CLKGN IO76PB5F5/CLKGP IO77NB5F5/CLKHN IO77PB5F5/CLKHP IO79NB5F5 IO79PB5F5 IO81NB5F5 IO81PB5F5 IO83NB5F5 IO83PB5F5 IO85NB5F5 IO85PB5F5 IO88NB5F5 IO88PB5F5 IO89NB5F5 IO89PB5F5 Bank 6 IO91NB6F6 IO91PB6F6 IO92NB6F6 IO92PB6F6 IO94NB6F6 IO94PB6F6 IO97NB6F6 IO97PB6F6 L4 M4 L3 M3 P2 N2 J4 K4 P7 P8 R6 R7 T5 T6 P5 P6 T3 T4 R3 R4 R1 T2 N4 N5 Pin Number T15 R12 R13 P11 P12 T11 T12 T13 R9 R10 T8 T9
256-Pin FBGA AX250 Function IO98NB6F6 IO98PB6F6 IO100NB6F6 IO100PB6F6 IO102NB6F6 IO102PB6F6 IO103NB6F6 IO103PB6F6 IO104NB6F6 IO104PB6F6 Bank 7 IO107NB7F7 IO107PB7F7 IO108NB7F7 IO108PB7F7 IO111NB7F7 IO111PB7F7 IO112NB7F7 IO112PB7F7 IO113NB7F7 IO114NB7F7 IO114PB7F7 IO115NB7F7 IO115PB7F7 IO116NB7F7 IO116PB7F7 IO117NB7F7 IO117PB7F7 IO118NB7F7 IO118PB7F7 IO119NB7F7 IO119PB7F7 Dedicated I/O VCCDA GND GND GND GND E4 A1 A16 B15 B2 J1 K1 G2 H2 G3 H3 E1 F1 G1 E2 F2 G4 H4 C1 D1 C2 B1 D2 D3 E3 F3 Pin Number N1 P1 L2 M2 L1 M1 J3 K3 J2 K2
256-Pin FBGA AX250 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND/LP PRA PRB PRC PRD TCK TDI Pin Number D15 E12 E5 F11 F6 G10 G7 G8 G9 H10 H7 H8 H9 J10 J7 J8 J9 K10 K7 K8 K9 L11 L6 M12 M5 P13 P3 R15 R2 T1 T16 D4 D8 C8 N9 P9 D5 C6
3 -1 6
v2.7
Axcelerator Family FPGAs
256-Pin FBGA AX250 Function TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA Pin Number C4 C3 C5 D14 F10 F4 F7 F8 F9 G11 G6 H11 H6 J11 J6 K11 K6 L10 L7 L8 L9 N3 P14 C7 D6 A10 D10 P10 N11 T7 N7 A11 A2 C13 D9 H1 J15 N14
256-Pin FBGA AX250 Function VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number N8 P4 R11 R5 E6 E7 E8 E10 E11 E9 F12 G12 H12 J12 K12 L12 M10 M11 M9 M6 M7 M8 J5 K5 L5 F5 G5 H5 A7 D7 B9 D11 T10 N10 R8 N6 A14
v2.7
3-17
Axcelerator Family FPGAs
324-Pin FBGA
A1 Ball Pad Corner 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V
Figure 3-4 * 324-Pin FBGA (Bottom View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
3 -1 8
v2.7
Axcelerator Family FPGAs
324-Pin FBGA AX125 Function Bank 0 IO00NB0F0 IO00PB0F0 IO01NB0F0 IO01PB0F0 IO02NB0F0 IO02PB0F0 IO03NB0F0 IO03PB0F0 IO04NB0F0 IO04PB0F0 IO05NB0F0 IO05PB0F0 IO06NB0F0 IO06PB0F0 IO07NB0F0/HCLKAN IO07PB0F0/HCLKAP IO08NB0F0/HCLKBN IO08PB0F0/HCLKBP Bank 1 IO09NB1F1/HCLKCN IO09PB1F1/HCLKCP IO10NB1F1/HCLKDN IO10PB1F1/HCLKDP IO11NB1F1 IO11PB1F1 IO12NB1F1 IO12PB1F1 IO13NB1F1 IO13PB1F1 IO14NB1F1 IO14PB1F1 IO15NB1F1 IO15PB1F1 IO16NB1F1 IO16PB1F1 IO17NB1F1 IO17PB1F1 D11 D10 C12 C11 A15 A14 B14 B13 A17 A16 D13 D12 C14 C13 B16 C15 E14 E13 C5 C4 A3 A2 C7 C6 B5 B4 A5 A4 A7 A6 B7 B6 C9 C8 B10 B9 Pin Number
324-Pin FBGA AX125 Function Bank 2 IO18NB2F2 IO18PB2F2 IO19NB2F2 IO19PB2F2 IO20NB2F2 IO20PB2F2 IO21NB2F2 IO21PB2F2 IO22NB2F2 IO22PB2F2 IO23NB2F2 IO23PB2F2 IO24NB2F2 IO24PB2F2 IO25NB2F2 IO25PB2F2 IO26NB2F2 IO26PB2F2 IO27NB2F2 IO27PB2F2 IO28NB2F2 IO28PB2F2 IO29NB2F2 IO29PB2F2 Bank 3 IO30NB3F3 IO30PB3F3 IO31NB3F3 IO31PB3F3 IO32NB3F3 IO32PB3F3 IO33NB3F3 IO33PB3F3 IO34NB3F3 IO34PB3F3 IO35NB3F3 IO35PB3F3 N18 M18 L18 K18 L16 L17 R18 P18 N15 M15 M16 M17 G14 F14 D16 D15 C18 B18 D17 C17 F17 E17 G16 F16 E18 D18 G18 F18 H17 G17 J16 H16 J18 H18 K17 J17 Pin Number
324-Pin FBGA AX125 Function IO36NB3F3 IO36PB3F3 IO37NB3F3 IO37PB3F3 IO38NB3F3 IO38PB3F3 IO39NB3F3 IO39PB3F3 IO40NB3F3 IO40PB3F3 IO41NB3F3 IO41PB3F3 Bank 4 IO42NB4F4 IO42PB4F4 IO43NB4F4 IO43PB4F4 IO44NB4F4 IO44PB4F4 IO45NB4F4 IO45PB4F4 IO46NB4F4 IO46PB4F4 IO47NB4F4 IO47PB4F4 IO48NB4F4 IO48PB4F4 IO49NB4F4/CLKEN IO49PB4F4/CLKEP IO50NB4F4/CLKFN IO50PB4F4/CLKFP Bank 5 IO51NB5F5/CLKGN IO51PB5F5/CLKGP IO52NB5F5/CLKHN IO52PB5F5/CLKHP IO53NB5F5 IO53PB5F5 R8 R9 T7 T8 U6 U7 T13 T14 U15 T15 U13 U14 V15 V16 V13 V14 V12 U12 V10 V11 T10 T11 U9 U10 Pin Number P16 N16 R17 P17 N14 M14 U18 T18 R16 T17 P13 P14
v2.7
3-19
Axcelerator Family FPGAs
324-Pin FBGA AX125 Function IO54NB5F5 IO54PB5F5 IO55NB5F5 IO55PB5F5 IO56NB5F5 IO56PB5F5 IO57NB5F5 IO57PB5F5 IO58NB5F5 IO58PB5F5 IO59NB5F5 IO59PB5F5 Bank 6 IO60NB6F6 IO60PB6F6 IO61NB6F6 IO61PB6F6 IO62NB6F6 IO62PB6F6 IO63NB6F6 IO63PB6F6 IO64NB6F6 IO64PB6F6 IO65NB6F6 IO65PB6F6 IO66NB6F6 IO66PB6F6 IO67NB6F6 IO67PB6F6 IO68NB6F6 IO68PB6F6 IO69NB6F6 IO69PB6F6 IO70NB6F6 IO70PB6F6 IO71NB6F6 IO71PB6F6 Bank 7 P5 P6 T2 U3 T1 U1 P1 R1 R3 P3 P2 R2 M3 N3 M2 N2 M1 N1 K4 L4 K1 L1 K3 L3 Pin Number V8 V9 V6 V7 U4 U5 T4 T5 V4 V5 V2 V3
324-Pin FBGA AX125 Function IO72NB7F7 IO72PB7F7 IO73NB7F7 IO73PB7F7 IO74NB7F7 IO74PB7F7 IO75NB7F7 IO75PB7F7 IO76NB7F7 IO76PB7F7 IO77NB7F7 IO77PB7F7 IO78NB7F7 IO78PB7F7 IO79NB7F7 IO79PB7F7 IO80NB7F7 IO80PB7F7 IO81NB7F7 IO81PB7F7 IO82NB7F7 IO82PB7F7 IO83NB7F7 IO83PB7F7 Dedicated I/O VCCDA GND GND GND GND GND GND GND GND GND GND GND GND F5 A1 A18 B17 B2 C16 C3 E16 F13 F6 G12 G7 H10 Pin Number H4 J4 K2 L2 H2 H1 H3 J3 F2 G2 F1 G1 D2 E2 F3 G3 E3 E4 D1 E1 D3 C2 B1 C1
324-Pin FBGA AX125 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND/LP NC NC NC NC NC NC NC NC NC NC Pin Number H11 H8 H9 J10 J11 J8 J9 K10 K11 K8 K9 L10 L11 L8 L9 M12 M7 N13 N6 R14 R4 T16 T3 U17 U2 V1 V18 E5 A10 A11 A12 A13 A8 A9 B12 F15 F4 G15
3 -2 0
v2.7
Axcelerator Family FPGAs
324-Pin FBGA AX125 Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA Pin Number G4 H14 H15 H5 J1 J14 J15 J5 K14 K15 K5 L14 L15 L5 M4 M5 N17 N4 N5 R12 R13 R6 R7 T12 T6 U16 V17 E9 D9 P10 R10 E6 D7 D5 D4 D6 E15 G10
324-Pin FBGA AX125 Function VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB1 Pin Number G11 G5 G8 G9 H12 H7 J12 J7 K12 K7 L12 L7 M10 M11 M8 M9 P4 R15 D8 E7 B11 E11 R11 P12 U8 P8 B3 D14 E10 J2 K16 P15 P9 R5 F7 F8 F9 F10
324-Pin FBGA AX125 Function VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number F11 F12 G13 H13 J13 K13 L13 M13 N10 N11 N12 N7 N8 N9 K6 L6 M6 G6 H6 J6 B8 E8 C10 E12 U11 P11 T9 P7 B15
v2.7
3-21
Axcelerator Family FPGAs
484-Pin FBGA
A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7654321 A B C D E F G H J K L M N P R T U V W Y AA AB
Figure 3-5 * 484-Pin FBGA (Bottom View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
3 -2 2
v2.7
Axcelerator Family FPGAs
484-Pin FBGA AX250 Function Bank 0 IO00NB0F0 IO00PB0F0 IO01NB0F0 IO01PB0F0 IO02NB0F0 IO02PB0F0 IO03NB0F0 IO03PB0F0 IO04NB0F0 IO04PB0F0 IO05NB0F0 IO05PB0F0 IO06NB0F0 IO06PB0F0 IO07NB0F0 IO07PB0F0 IO08NB0F0 IO08PB0F0 IO09NB0F0 IO09PB0F0 IO10NB0F0 IO10PB0F0 IO11NB0F0 IO11PB0F0 IO12NB0F0/HCLKAN IO12PB0F0/HCLKAP IO13NB0F0/HCLKBN IO13PB0F0/HCLKBP Bank 1 IO14NB1F1/HCLKCN IO14PB1F1/HCLKCP IO15NB1F1/HCLKDN IO15PB1F1/HCLKDP IO16NB1F1 IO16PB1F1 IO17NB1F1 IO17PB1F1 F13 F12 E14 E13 C13 C12 B14 B13 D7 D6 E7 E6 C5 C4 C7 C6 E9 E8 D9 D8 B7 B6 C9 C8 A7 A6 B9 B8 A9 A8 B10 A10 E11 E10 D12 D11 Pin Number
484-Pin FBGA AX250 Function IO18NB1F1 IO18PB1F1 IO19NB1F1 IO19PB1F1 IO20NB1F1 IO20PB1F1 IO21NB1F1 IO21PB1F1 IO22NB1F1 IO22PB1F1 IO23NB1F1 IO23PB1F1 IO24NB1F1 IO24PB1F1 IO25NB1F1 IO25PB1F1 IO26NB1F1 IO26PB1F1 IO27NB1F1 IO27PB1F1 Bank 2 IO28NB2F2 IO28PB2F2 IO29NB2F2 IO29PB2F2 IO30NB2F2 IO30PB2F2 IO31NB2F2 IO31PB2F2 IO32NB2F2 IO32PB2F2 IO33NB2F2 IO33PB2F2 IO34NB2F2 IO34PB2F2 IO35NB2F2 IO35PB2F2 IO36NB2F2 F19 E19 J16 H16 E20 D20 J17 H17 G20 F20 H19 G19 E22 D22 J18 H18 G21 Pin Number A14 A13 A16 A15 B16 B15 C17 C16 F15 F14 D16 D15 E16 E15 F18 F17 D18 E17 G16 G15
484-Pin FBGA AX250 Function IO36PB2F2 IO37NB2F2 IO37PB2F2 IO38NB2F2 IO38PB2F2 IO39NB2F2 IO39PB2F2 IO40NB2F2 IO40PB2F2 IO41NB2F2 IO41PB2F2 IO42NB2F2 IO42PB2F2 IO43NB2F2 IO43PB2F2 IO44NB2F2 IO44PB2F2 Bank 3 IO45NB3F3 IO45PB3F3 IO46NB3F3 IO46PB3F3 IO47NB3F3 IO47PB3F3 IO48NB3F3 IO48PB3F3 IO49NB3F3 IO49PB3F3 IO50NB3F3 IO50PB3F3 IO51NB3F3 IO51PB3F3 IO52NB3F3 IO52PB3F3 IO53NB3F3 IO53PB3F3 IO54NB3F3 IO54PB3F3 M19 L19 M21 L21 N17 M17 N18 N19 N16 M16 N20 M20 P21 N21 P18 P19 R20 P20 T21 R21 Pin Number F21 K19 J19 J20 H20 L16 K16 J21 H21 L17 K17 J22 H22 L18 K18 L20 K20
v2.7
3-23
Axcelerator Family FPGAs
484-Pin FBGA AX250 Function IO55NB3F3 IO55PB3F3 IO56NB3F3 IO56PB3F3 IO57NB3F3 IO57PB3F3 IO58NB3F3 IO58PB3F3 IO59NB3F3 IO59PB3F3 IO60NB3F3 IO60PB3F3 IO61NB3F3 IO61PB3F3 Bank 4 IO62NB4F4 IO62PB4F4 IO63NB4F4 IO63PB4F4 IO64NB4F4 IO64PB4F4 IO65NB4F4 IO65PB4F4 IO66NB4F4 IO66PB4F4 IO67NB4F4 IO67PB4F4 IO68NB4F4 IO68PB4F4 IO69NB4F4 IO69PB4F4 IO70NB4F4 IO70PB4F4 IO71NB4F4 IO71PB4F4 IO72NB4F4 IO72PB4F4 IO73NB4F4 T15 T16 W17 V17 V15 V16 Y19 W18 AB18 AB19 W15 W16 U14 U15 AA16 AA17 AB14 AB15 Y14 W14 AA14 AA15 AA13 Pin Number R17 P17 U20 T20 T18 R18 U19 T19 R16 P16 W20 V20 U18 V19
484-Pin FBGA AX250 Function IO73PB4F4 IO74NB4F4/CLKEN IO74PB4F4/CLKEP IO75NB4F4/CLKFN IO75PB4F4/CLKFP Bank 5 IO76NB5F5/CLKGN IO76PB5F5/CLKGP IO77NB5F5/CLKHN IO77PB5F5/CLKHP IO78NB5F5 IO78PB5F5 IO79NB5F5 IO79PB5F5 IO80NB5F5 IO80PB5F5 IO81NB5F5 IO81PB5F5 IO82NB5F5 IO82PB5F5 IO83NB5F5 IO83PB5F5 IO84NB5F5 IO84PB5F5 IO85NB5F5 IO85PB5F5 IO86NB5F5 IO86PB5F5 IO87NB5F5 IO87PB5F5 IO88NB5F5 IO88PB5F5 IO89NB5F5 IO89PB5F5 Bank 6 IO90NB6F6 IO90PB6F6 IO91NB6F6 V4 W5 P7 U10 U11 V9 V10 AA9 AA10 AB9 AB10 AA7 AA8 W8 W9 AB5 AB6 AA5 AA6 U8 U9 Y6 Y7 W6 W7 Y4 Y5 V6 V7 T7 T8 Pin Number AB13 V12 V13 W11 W12
484-Pin FBGA AX250 Function IO91PB6F6 IO92NB6F6 IO92PB6F6 IO93NB6F6 IO93PB6F6 IO94NB6F6 IO94PB6F6 IO95NB6F6 IO95PB6F6 IO96NB6F6 IO96PB6F6 IO97NB6F6 IO97PB6F6 IO98NB6F6 IO98PB6F6 IO99NB6F6 IO99PB6F6 IO100NB6F6 IO100PB6F6 IO101NB6F6 IO101PB6F6 IO102NB6F6 IO102PB6F6 IO103NB6F6 IO103PB6F6 IO104NB6F6 IO104PB6F6 IO105NB6F6 IO105PB6F6 IO106NB6F6 IO106PB6F6 Bank 7 IO107NB7F7 IO107PB7F7 IO108NB7F7 IO108PB7F7 IO109NB7F7 IO109PB7F7 M2 N1 L3 L2 K2 K1 Pin Number R7 U5 T5 P6 R6 T4 U4 P5 R5 T3 U3 P3 R3 R2 T2 P4 R4 P1 R1 M7 N7 N2 P2 M6 N6 M4 N4 M5 N5 M3 N3
3 -2 4
v2.7
Axcelerator Family FPGAs
484-Pin FBGA AX250 Function IO110NB7F7 IO110PB7F7 IO111NB7F7 IO111PB7F7 IO112NB7F7 IO112PB7F7 IO113NB7F7 IO113PB7F7 IO114NB7F7 IO114PB7F7 IO115NB7F7 IO115PB7F7 IO116NB7F7 IO116PB7F7 IO117NB7F7 IO117PB7F7 IO118NB7F7 IO118PB7F7 IO119NB7F7 IO119PB7F7 IO120NB7F7 IO120PB7F7 IO121NB7F7 IO121PB7F7 IO122NB7F7 IO122PB7F7 IO123NB7F7 IO123PB7F7 Dedicated I/O VCCDA GND GND GND GND GND GND GND GND H7 A1 A11 A12 A2 A21 A22 AA1 AA2 Pin Number K5 L5 K6 L6 K4 K3 K7 L7 H1 J1 H2 J2 H4 J4 H5 J5 F2 G2 H6 J6 F1 G1 F4 G4 G5 G6 F5 E4
484-Pin FBGA AX250 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AA21 AA22 AB1 AB11 AB12 AB2 AB21 AB22 B1 B2 B21 B22 C20 C3 D19 D4 E18 E5 G18 H15 H8 J14 J9 K10 K11 K12 K13 L1 L10 L11 L12 L13 L22 M1 M10 M11 M12 M13
484-Pin FBGA AX250 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND/LP NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin Number M22 N10 N11 N12 N13 P14 P9 R15 R8 U16 U6 V18 V5 W19 W4 Y20 Y3 G7 A17 A18 A19 A4 A5 AA11 AA12 AA18 AA19 AA4 AB16 AB17 AB4 AB7 AB8 B11 B12 B17 B18 B19
v2.7
3-25
Axcelerator Family FPGAs
484-Pin FBGA AX250 Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin Number B4 B5 C10 C11 C14 C15 C18 C19 D1 D2 D21 D3 E1 E2 E21 E3 F22 F3 G22 G3 H3 J3 K21 K22 N22 P22 R19 R22 T1 T22 U1 U2 U21 U22 V1 V2 V21 V22
484-Pin FBGA AX250 Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA Pin Number V3 W1 W2 W21 W22 W3 Y10 Y11 Y12 Y13 Y15 Y16 Y17 Y18 Y8 Y9 G11 F11 T12 U12 G8 F9 F7 F6 F8 G17 J10 J11 J12 J13 J7 K14 K9 L14 L9 M14 M9 N14
484-Pin FBGA AX250 Function VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 Pin Number N9 P10 P11 P12 P13 T6 U17 F10 G9 D13 G13 U13 T14 W10 T10 D14 D5 F16 G12 L4 M18 T11 T17 U7 V14 V8 A3 B3 H10 H11 H9 A20 B20 H12 H13 H14 C21 C22
3 -2 6
v2.7
Axcelerator Family FPGAs
484-Pin FBGA AX250 Function VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number J15 K15 L15 M15 N15 P15 Y21 Y22 AA20 AB20 R12 R13 R14 AA3 AB3 R10 R11 R9 M8 N8 P8 Y1 Y2 C1 C2 J8 K8 L8 D10 G10 E12 G14 W13 T13 V11 T9 D17
484-Pin FBGA AX500 Function Bank 0 IO00NB0F0 IO00PB0F0 IO01NB0F0 IO01PB0F0 IO02NB0F0 IO02PB0F0 IO03NB0F0 IO03PB0F0 IO04NB0F0 IO04PB0F0 IO05NB0F0 IO05PB0F0 IO06NB0F0 IO06PB0F0 IO07NB0F0 IO07PB0F0 IO08NB0F0 IO08PB0F0 IO10NB0F0 IO10PB0F0 IO11NB0F0 IO11PB0F0 IO12NB0F1 IO12PB0F1 IO13NB0F1 IO13PB0F1 IO14NB0F1 IO14PB0F1 IO15NB0F1 IO15PB0F1 IO16NB0F1 IO16PB0F1 IO18NB0F1 IO18PB0F1 IO19NB0F1/HCLKAN IO19PB0F1/HCLKAP IO20NB0F1/HCLKBN E3 D3 E7 E6 C5 C4 D7 D6 B5 B4 C7 C6 A5 A4 A7 A6 B7 B6 B9 B8 E9 E8 D9 D8 C9 C8 A9 A8 B10 A10 B12 B11 C13 C12 E11 E10 D12 Pin Number
484-Pin FBGA AX500 Function IO20PB0F1/HCLKBP Bank 1 IO21NB1F2/HCLKCN IO21PB1F2/HCLKCP IO22NB1F2/HCLKDN IO22PB1F2/HCLKDP IO24NB1F2 IO24PB1F2 IO25NB1F2 IO25PB1F2 IO26NB1F2 IO27NB1F2 IO27PB1F2 IO28NB1F2 IO28PB1F2 IO29NB1F2 IO29PB1F2 IO30NB1F2 IO30PB1F2 IO31NB1F2 IO31PB1F2 IO32NB1F3 IO32PB1F3 IO33NB1F3 IO33PB1F3 IO34NB1F3 IO34PB1F3 IO35NB1F3 IO35PB1F3 IO36NB1F3 IO36PB1F3 IO37NB1F3 IO37PB1F3 IO38NB1F3 IO38PB1F3 IO39NB1F3 IO39PB1F3 IO40NB1F3 F13 F12 E14 E13 A14 A13 B14 B13 C15 A16 A15 B16 B15 D16 D15 A18 A17 F15 F14 C17 C16 E16 E15 B18 B17 B19 A19 C19 C18 F18 F17 D18 E17 E21 D21 E20 Pin Number D11
v2.7
3-27
Axcelerator Family FPGAs
484-Pin FBGA AX500 Function IO40PB1F3 IO41NB1F3 IO41PB1F3 Bank 2 IO42NB2F4 IO42PB2F4 IO43NB2F4 IO43PB2F4 IO44NB2F4 IO44PB2F4 IO45NB2F4 IO45PB2F4 IO46NB2F4 IO46PB2F4 IO47NB2F4 IO47PB2F4 IO48NB2F4 IO48PB2F4 IO49NB2F4 IO49PB2F4 IO50NB2F4 IO50PB2F4 IO51NB2F4 IO51PB2F4 IO52NB2F5 IO52PB2F5 IO53NB2F5 IO53PB2F5 IO54NB2F5 IO54PB2F5 IO55NB2F5 IO55PB2F5 IO56NB2F5 IO56PB2F5 IO58NB2F5 IO58PB2F5 IO59NB2F5 IO59PB2F5 F19 E19 J16 H16 E22 D22 H19 G19 G22 F22 J17 H17 G20 F20 J18 H18 G21 F21 K19 J19 J21 H21 J20 H20 J22 H22 L17 K17 K21 K22 L20 K20 L18 K18 Pin Number D20 G16 G15
484-Pin FBGA AX500 Function IO60NB2F5 IO60PB2F5 IO61NB2F5 IO61PB2F5 IO62NB2F5 IO62PB2F5 Bank 3 IO63NB3F6 IO63PB3F6 IO64NB3F6 IO64PB3F6 IO65NB3F6 IO65PB3F6 IO66NB3F6 IO66PB3F6 IO67NB3F6 IO67PB3F6 IO68NB3F6 IO68PB3F6 IO69NB3F6 IO69PB3F6 IO70NB3F6 IO70PB3F6 IO71NB3F6 IO71PB3F6 IO72NB3F6 IO72PB3F6 IO73PB3F6 IO74NB3F7 IO74PB3F7 IO75NB3F7 IO75PB3F7 IO76NB3F7 IO76PB3F7 IO77NB3F7 IO77PB3F7 IO78NB3F7 IO78PB3F7 N16 M16 P22 N22 N20 M20 P21 N21 N18 N19 T22 R22 N17 M17 T21 R21 P18 P19 R20 P20 R19 V21 U21 V22 U22 U20 T20 R17 P17 W21 W22 Pin Number M21 L21 L16 K16 M19 L19
484-Pin FBGA AX500 Function IO79NB3F7 IO79PB3F7 IO80NB3F7 IO80PB3F7 IO81NB3F7 IO81PB3F7 IO82NB3F7 IO82PB3F7 IO83NB3F7 IO83PB3F7 Bank 4 IO84NB4F8 IO84PB4F8 IO85NB4F8 IO85PB4F8 IO86NB4F8 IO86PB4F8 IO87NB4F8 IO87PB4F8 IO88NB4F8 IO88PB4F8 IO89NB4F8 IO89PB4F8 IO90NB4F8 IO90PB4F8 IO91NB4F8 IO91PB4F8 IO92PB4F8 IO93NB4F8 IO93PB4F8 IO94NB4F9 IO94PB4F9 IO95NB4F9 IO95PB4F9 IO96NB4F9 IO96PB4F9 IO97NB4F9 IO97PB4F9 AB18 AB19 T15 T16 AA18 AA19 W17 V17 Y19 W18 U14 U15 Y17 Y18 V15 V16 AB17 Y15 Y16 AA16 AA17 AB14 AB15 W15 W16 AA13 AB13 Pin Number T18 R18 W20 V20 U19 T19 U18 V19 R16 P16
3 -2 8
v2.7
Axcelerator Family FPGAs
484-Pin FBGA AX500 Function IO98NB4F9 IO98PB4F9 IO100NB4F9 IO100PB4F9 IO101NB4F9 IO101PB4F9 IO102NB4F9 IO102PB4F9 IO103NB4F9/CLKEN IO103PB4F9/CLKEP IO104NB4F9/CLKFN IO104PB4F9/CLKFP Bank 5 IO105NB5F10/CLKGN IO105PB5F10/CLKGP IO106NB5F10/CLKHN IO106PB5F10/CLKHP IO107NB5F10 IO107PB5F10 IO108NB5F10 IO108PB5F10 IO110NB5F10 IO110PB5F10 IO111NB5F10 IO111PB5F10 IO112NB5F10 IO113NB5F10 IO113PB5F10 IO114NB5F11 IO114PB5F11 IO115NB5F11 IO115PB5F11 IO116NB5F11 IO116PB5F11 IO117NB5F11 IO117PB5F11 IO118NB5F11 IO118PB5F11 U10 U11 V9 V10 Y10 Y11 AA9 AA10 AB9 AB10 Y8 Y9 AB7 W8 W9 AA7 AA8 AB5 AB6 Y6 Y7 U8 U9 AA5 AA6 Pin Number AA14 AA15 Y14 W14 Y12 Y13 AA11 AA12 V12 V13 W11 W12
484-Pin FBGA AX500 Function IO119NB5F11 IO119PB5F11 IO120NB5F11 IO120PB5F11 IO121NB5F11 IO121PB5F11 IO122NB5F11 IO122PB5F11 IO123NB5F11 IO123PB5F11 IO124NB5F11 IO124PB5F11 IO125NB5F11 IO125PB5F11 Bank 6 IO126NB6F12 IO126PB6F12 IO127NB6F12 IO127PB6F12 IO128NB6F12 IO128PB6F12 IO129NB6F12 IO129PB6F12 IO130NB6F12 IO130PB6F12 IO131NB6F12 IO131PB6F12 IO132NB6F12 IO132PB6F12 IO133NB6F12 IO134NB6F12 IO134PB6F12 IO135NB6F12 IO135PB6F12 IO136NB6F13 IO136PB6F13 IO138NB6F13 IO138PB6F13 V2 W2 P7 R7 V1 W1 U5 T5 T1 U1 P6 R6 T4 U4 U2 T3 U3 P5 R5 R2 T2 P4 R4 Pin Number AA4 AB4 Y4 Y5 W6 W7 V3 W3 T7 T8 V4 W5 V6 V7
484-Pin FBGA AX500 Function IO139NB6F13 IO139PB6F13 IO140NB6F13 IO140PB6F13 IO141NB6F13 IO141PB6F13 IO142NB6F13 IO142PB6F13 IO143NB6F13 IO143PB6F13 IO144NB6F13 IO144PB6F13 IO145NB6F13 IO145PB6F13 IO146NB6F13 IO146PB6F13 Bank 7 IO147NB7F14 IO147PB7F14 IO148NB7F14 IO148PB7F14 IO149NB7F14 IO149PB7F14 IO150NB7F14 IO150PB7F14 IO151NB7F14 IO151PB7F14 IO152NB7F14 IO152PB7F14 IO153NB7F14 IO153PB7F14 IO154NB7F14 IO154PB7F14 IO155NB7F14 IO155PB7F14 IO156NB7F14 IO156PB7F14 IO157NB7F14 K7 L7 M2 N1 K5 L5 L3 L2 K6 L6 K2 K1 K4 K3 H3 J3 H5 J5 H4 J4 H2 Pin Number N2 P2 P3 R3 M6 N6 P1 R1 M5 N5 M4 N4 M7 N7 M3 N3
v2.7
3-29
Axcelerator Family FPGAs
484-Pin FBGA AX500 Function IO157PB7F14 IO158NB7F15 IO158PB7F15 IO159NB7F15 IO159PB7F15 IO160NB7F15 IO160PB7F15 IO161NB7F15 IO161PB7F15 IO162NB7F15 IO162PB7F15 IO163NB7F15 IO163PB7F15 IO164NB7F15 IO164PB7F15 IO165NB7F15 IO165PB7F15 IO166NB7F15 IO166PB7F15 IO167NB7F15 IO167PB7F15 Dedicated I/O VCCDA GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND H7 A1 A11 A12 A2 A21 A22 AA1 AA2 AA21 AA22 AB1 AB11 AB12 AB2 AB21 Pin Number J2 H1 J1 F1 G1 F2 G2 H6 J6 F3 G3 G5 G6 D1 E1 F4 G4 D2 E2 F5 E4
484-Pin FBGA AX500 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AB22 B1 B2 B21 B22 C20 C3 D19 D4 E18 E5 G18 H15 H8 J14 J9 K10 K11 K12 K13 L1 L10 L11 L12 L13 L22 M1 M10 M11 M12 M13 M22 N10 N11 N12 N13 P14 P9
484-Pin FBGA AX500 Function GND GND GND GND GND GND GND GND GND GND GND/LP NC NC NC NC NC PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA Pin Number R15 R8 U16 U6 V18 V5 W19 W4 Y20 Y3 G7 AB8 AB16 C10 C11 C14 G11 F11 T12 U12 G8 F9 F7 F6 F8 G17 J10 J11 J12 J13 J7 K14 K9 L14 L9 M14 M9 N14
3 -3 0
v2.7
Axcelerator Family FPGAs
484-Pin FBGA AX500 Function VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 Pin Number N9 P10 P11 P12 P13 T6 U17 F10 G9 D13 G13 U13 T14 W10 T10 D14 D5 F16 G12 L4 M18 T11 T17 U7 V14 V8 A3 B3 H10 H11 H9 A20 B20 H12 H13 H14 C21 C22
484-Pin FBGA AX500 Function VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number J15 K15 L15 M15 N15 P15 Y21 Y22 AA20 AB20 R12 R13 R14 AA3 AB3 R10 R11 R9 M8 N8 P8 Y1 Y2 C1 C2 J8 K8 L8 D10 G10 E12 G14 W13 T13 V11 T9 D17
v2.7
3-31
Axcelerator Family FPGAs
484-Pin FBGA AX1000 Function Bank 0 IO01NB0F0 IO01PB0F0 IO02NB0F0 IO02PB0F0 IO05NB0F0 IO05PB0F0 IO06NB0F0 IO06PB0F0 IO12NB0F1 IO12PB0F1 IO13NB0F1 IO13PB0F1 IO14NB0F1 IO14PB0F1 IO15NB0F1 IO15PB0F1 IO16NB0F1 IO16PB0F1 IO17NB0F1 IO17PB0F1 IO18NB0F1 IO18PB0F1 IO19NB0F1 IO19PB0F1 IO20NB0F1 IO20PB0F1 IO21NB0F1 IO21PB0F1 IO22NB0F2 IO22PB0F2 IO23NB0F2 IO23PB0F2 IO26NB0F2 IO26PB0F2 IO29NB0F2 IO29PB0F2 IO30NB0F2/HCLKAN IO30PB0F2/HCLKAP IO31NB0F2/HCLKBN IO31PB0F2/HCLKBP Bank 1 IO32NB1F3/HCLKCN F13 E3 D3 E7 E6 D2 E2 C5 C4 D7 D6 B5 B4 E9 E8 C7 C6 A5 A4 B7 B6 A7 A6 C9 C8 D9 D8 B9 B8 A9 A8 B10 A10 A14 A13 B12 B11 E11 E10 D12 D11 Pin Number
484-Pin FBGA AX1000 Function IO32PB1F3/HCLKCP IO33NB1F3/HCLKDN IO33PB1F3/HCLKDP IO34NB1F3 IO34PB1F3 IO37NB1F3 IO37PB1F3 IO38NB1F3 IO38PB1F3 IO40NB1F3 IO42NB1F4 IO42PB1F4 IO43NB1F4 IO43PB1F4 IO44NB1F4 IO44PB1F4 IO45NB1F4 IO45PB1F4 IO46NB1F4 IO46PB1F4 IO48NB1F4 IO48PB1F4 IO49NB1F4 IO49PB1F4 IO50NB1F4 IO50PB1F4 IO51NB1F4 IO51PB1F4 IO52NB1F4 IO52PB1F4 IO57NB1F5 IO57PB1F5 IO60NB1F5 IO60PB1F5 IO61NB1F5 IO61PB1F5 IO63NB1F5 IO63PB1F5 Bank 2 IO64NB2F6 IO64PB2F6 IO67NB2F6 IO67PB2F6 F18 F17 F19 E19 Pin Number F12 E14 E13 C13 C12 B14 B13 A16 A15 C15 A18 A17 B16 B15 B18 B17 B19 A19 C19 C18 F15 F14 D16 D15 C17 C16 E22 D22 E16 E15 E21 D21 G16 G15 D18 E17 E20 D20
484-Pin FBGA AX1000 Function IO68NB2F6 IO68PB2F6 IO70NB2F6 IO70PB2F6 IO74NB2F7 IO74PB2F7 IO75NB2F7 IO75PB2F7 IO79NB2F7 IO79PB2F7 IO80NB2F7 IO80PB2F7 IO84NB2F7 IO84PB2F7 IO85NB2F8 IO85PB2F8 IO86NB2F8 IO86PB2F8 IO87NB2F8 IO87PB2F8 IO88NB2F8 IO88PB2F8 IO89NB2F8 IO89PB2F8 IO90NB2F8 IO90PB2F8 IO91NB2F8 IO91PB2F8 IO93NB2F8 IO93PB2F8 IO94NB2F8 IO94PB2F8 IO95NB2F8 IO95PB2F8 Bank 3 IO96NB3F9 IO96PB3F9 IO97NB3F9 IO97PB3F9 IO98NB3F9 IO98PB3F9 IO99NB3F9 IO99PB3F9 N16 M16 M19 L19 P22 N22 N20 M20 Pin Number J16 H16 J17 H17 J18 H18 G20 F20 H19 G19 L16 K16 L17 K17 G21 F21 G22 F22 J20 H20 L18 K18 K19 J19 J21 H21 J22 H22 K21 K22 L20 K20 M21 L21
3 -3 2
v2.7
Axcelerator Family FPGAs
484-Pin FBGA AX1000 Function IO100NB3F9 IO100PB3F9 IO101NB3F9 IO101PB3F9 IO103NB3F9 IO103PB3F9 IO104NB3F9 IO104PB3F9 IO105NB3F9 IO105PB3F9 IO106NB3F9 IO106PB3F9 IO107NB3F10 IO107PB3F10 IO110NB3F10 IO110PB3F10 IO113NB3F10 IO113PB3F10 IO114NB3F10 IO114PB3F10 IO116PB3F10 IO117NB3F10 IO117PB3F10 IO118NB3F11 IO118PB3F11 IO121NB3F11 IO121PB3F11 IO124NB3F11 IO124PB3F11 IO127NB3F11 IO127PB3F11 Bank 4 IO129PB4F12 IO132NB4F12 IO132PB4F12 IO133NB4F12 IO133PB4F12 IO135NB4F12 IO135PB4F12 IO138NB4F12 IO138PB4F12 IO139NB4F13 IO139PB4F13 AB17 Y19 W18 W17 V17 T15 T16 Y17 Y18 V15 V16 Pin Number N17 M17 P21 N21 R20 P20 N18 N19 T22 R22 R17 P17 T21 R21 V22 U22 V21 U21 P18 P19 R19 U20 T20 T18 R18 U19 T19 R16 P16 W21 W22
484-Pin FBGA AX1000 Function IO140NB4F13 IO140PB4F13 IO142NB4F13 IO142PB4F13 IO143NB4F13 IO143PB4F13 IO144NB4F13 IO144PB4F13 IO145NB4F13 IO145PB4F13 IO146NB4F13 IO146PB4F13 IO147NB4F13 IO147PB4F13 IO149NB4F13 IO149PB4F13 IO150NB4F13 IO150PB4F13 IO152NB4F14 IO152PB4F14 IO154NB4F14 IO154PB4F14 IO155NB4F14 IO155PB4F14 IO158NB4F14 IO158PB4F14 IO159NB4F14/CLKEN IO159PB4F14/CLKEP IO160NB4F14/CLKFN IO160PB4F14/CLKFP Bank 5 IO161NB5F15/CLKGN IO161PB5F15/CLKGP IO162NB5F15/CLKHN IO162PB5F15/CLKHP IO163NB5F15 IO163PB5F15 IO167NB5F15 IO167PB5F15 IO169NB5F15 IO169PB5F15 IO170NB5F15 IO170PB5F15 U10 U11 V9 V10 Y10 Y11 AA11 AA12 AA9 AA10 AB9 AB10 Pin Number U18 V19 W20 V20 W15 W16 AA18 AA19 U14 U15 Y15 Y16 AB18 AB19 Y14 W14 AA16 AA17 AA14 AA15 AB14 AB15 AA13 AB13 Y12 Y13 V12 V13 W11 W12
484-Pin FBGA AX1000 Function IO171NB5F16 IO171PB5F16 IO172NB5F16 IO172PB5F16 IO173NB5F16 IO173PB5F16 IO174NB5F16 IO174PB5F16 IO175NB5F16 IO175PB5F16 IO176NB5F16 IO176PB5F16 IO177NB5F16 IO177PB5F16 IO178NB5F16 IO178PB5F16 IO179NB5F16 IO179PB5F16 IO180NB5F16 IO180PB5F16 IO181NB5F17 IO181PB5F17 IO184NB5F17 IO187NB5F17 IO187PB5F17 IO188NB5F17 IO188PB5F17 IO192NB5F17 IO192PB5F17 Bank 6 IO194NB6F18 IO194PB6F18 IO195NB6F18 IO195PB6F18 IO200NB6F18 IO200PB6F18 IO201NB6F18 IO201PB6F18 IO203NB6F19 IO204NB6F19 IO204PB6F19 IO205NB6F19 IO205PB6F19 V2 W2 U5 T5 T4 U4 P6 R6 U2 T3 U3 P5 R5 Pin Number W8 W9 Y8 Y9 U8 U9 AA7 AA8 AB5 AB6 AA5 AA6 AA4 AB4 Y6 Y7 T7 T8 W6 W7 Y4 Y5 AB7 V3 W3 V4 W5 V6 V7
v2.7
3-33
Axcelerator Family FPGAs
484-Pin FBGA AX1000 Function IO208NB6F19 IO208PB6F19 IO209NB6F19 IO209PB6F19 IO212NB6F19 IO212PB6F19 IO214NB6F20 IO214PB6F20 IO215NB6F20 IO215PB6F20 IO216NB6F20 IO216PB6F20 IO217NB6F20 IO217PB6F20 IO219NB6F20 IO219PB6F20 IO220NB6F20 IO220PB6F20 IO221NB6F20 IO221PB6F20 IO222NB6F20 IO222PB6F20 IO223NB6F20 IO223PB6F20 IO224NB6F20 IO224PB6F20 Bank 7 IO225NB7F21 IO225PB7F21 IO226NB7F21 IO226PB7F21 IO228NB7F21 IO228PB7F21 IO229NB7F21 IO229PB7F21 IO230NB7F21 IO230PB7F21 IO231NB7F21 IO231PB7F21 IO232NB7F21 IO232PB7F21 IO233NB7F21 IO233PB7F21 M2 N1 K2 K1 L3 L2 K5 L5 H1 J1 H2 J2 K4 K3 K6 L6 Pin Number V1 W1 P7 R7 P4 R4 P3 R3 M6 N6 R2 T2 T1 U1 M5 N5 P1 R1 N2 P2 M3 N3 M7 N7 M4 N4
484-Pin FBGA AX1000 Function IO234NB7F21 IO234PB7F21 IO235NB7F21 IO235PB7F21 IO236NB7F22 IO236PB7F22 IO237NB7F22 IO237PB7F22 IO241NB7F22 IO241PB7F22 IO242NB7F22 IO242PB7F22 IO243NB7F22 IO243PB7F22 IO246NB7F22 IO246PB7F22 IO250NB7F23 IO250PB7F23 IO253NB7F23 IO253PB7F23 IO254NB7F23 IO254PB7F23 IO257NB7F23 IO257PB7F23 Dedicated I/O VCCDA GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND H7 A1 A11 A12 A2 A21 A22 AA1 AA2 AA21 AA22 AB1 AB11 AB12 AB2 AB21 AB22 B1 Pin Number F1 G1 F2 G2 H3 J3 K7 L7 H6 J6 H4 J4 H5 J5 F3 G3 F4 G4 G5 G6 D1 E1 F5 E4
484-Pin FBGA AX1000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number B2 B21 B22 C20 C3 D19 D4 E18 E5 G18 H15 H8 J14 J9 K10 K11 K12 K13 L1 L10 L11 L12 L13 L22 M1 M10 M11 M12 M13 M22 N10 N11 N12 N13 P14 P9 R15 R8 U16 U6 V18 V5 W19
3 -3 4
v2.7
Axcelerator Family FPGAs
484-Pin FBGA AX1000 Function GND GND GND GND/LP PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCCDA VCCDA Pin Number W4 Y20 Y3 G7 G11 F11 T12 U12 G8 F9 F7 F6 F8 G17 J10 J11 J12 J13 J7 K14 K9 L14 L9 M14 M9 N14 N9 P10 P11 P12 P13 T6 U17 F10 G9 D13 G13 U13 T14 W10 T10 AB16 AB8
484-Pin FBGA AX1000 Function VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB5 Pin Number C10 C11 C14 D14 D5 F16 G12 L4 M18 T11 T17 U7 V14 V8 A3 B3 H10 H11 H9 A20 B20 H12 H13 H14 C21 C22 J15 K15 L15 M15 N15 P15 Y21 Y22 AA20 AB20 R12 R13 R14 AA3 AB3 R10 R11
484-Pin FBGA AX1000 Function VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number R9 M8 N8 P8 Y1 Y2 C1 C2 J8 K8 L8 D10 G10 E12 G14 W13 T13 V11 T9 D17
v2.7
3-35
Axcelerator Family FPGAs
676-Pin FBGA
A1 Ball Pad Corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 54 3 21 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
Figure 3-6 * 676-Pin FBGA (Bottom View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
3 -3 6
v2.7
Axcelerator Family FPGAs
676-Pin FBGA AX500 Function Bank 0 IO00NB0F0 IO00PB0F0 IO01NB0F0 IO01PB0F0 IO02NB0F0 IO02PB0F0 IO03NB0F0 IO03PB0F0 IO04NB0F0 IO04PB0F0 IO05NB0F0 IO05PB0F0 IO06NB0F0 IO06PB0F0 IO07NB0F0 IO07PB0F0 IO08NB0F0 IO08PB0F0 IO09NB0F0 IO09PB0F0 IO10NB0F0 IO10PB0F0 IO11NB0F0 IO11PB0F0 IO12NB0F1 IO12PB0F1 IO13NB0F1 IO13PB0F1 IO14NB0F1 IO14PB0F1 IO15NB0F1 IO15PB0F1 IO16NB0F1 IO16PB0F1 IO17NB0F1 IO17PB0F1 IO18NB0F1 IO18PB0F1 F8 E8 A5 A4 E7 E6 D6 D5 B5 C5 B6 C6 C7 D7 A7 A6 C8 D8 F10 F9 B8 B7 D10 E10 B9 C9 F11 G11 D11 E11 B10 C10 A10 A9 F12 G12 C12 C11 Pin Number
676-Pin FBGA AX500 Function IO19NB0F1/HCLKAN IO19PB0F1/HCLKAP IO20NB0F1/HCLKBN IO20PB0F1/HCLKBP Bank 1 IO21NB1F2/HCLKCN IO21PB1F2/HCLKCP IO22NB1F2/HCLKDN IO22PB1F2/HCLKDP IO23NB1F2 IO23PB1F2 IO24NB1F2 IO24PB1F2 IO25NB1F2 IO25PB1F2 IO26NB1F2 IO26PB1F2 IO27NB1F2 IO27PB1F2 IO28NB1F2 IO28PB1F2 IO29NB1F2 IO29PB1F2 IO30NB1F2 IO30PB1F2 IO31NB1F2 IO31PB1F2 IO32NB1F3 IO32PB1F3 IO33NB1F3 IO33PB1F3 IO34NB1F3 IO34PB1F3 IO35NB1F3 IO35PB1F3 IO36NB1F3 IO36PB1F3 IO37NB1F3 IO37PB1F3 C15 C14 A15 B15 F15 G15 B16 A16 A18 A17 D16 E16 F16 G16 C18 C17 B19 B18 D19 C19 F17 E17 B20 A20 B22 B21 D20 C20 D21 C21 D22 C22 F19 E19 Pin Number A12 B12 C13 B13
676-Pin FBGA AX500 Function IO38NB1F3 IO38PB1F3 IO39NB1F3 IO39PB1F3 IO40NB1F3 IO40PB1F3 IO41NB1F3 IO41PB1F3 Bank 2 IO42NB2F4 IO42PB2F4 IO43NB2F4 IO43PB2F4 IO44NB2F4 IO44PB2F4 IO45NB2F4 IO45PB2F4 IO46NB2F4 IO46PB2F4 IO47NB2F4 IO47PB2F4 IO48NB2F4 IO48PB2F4 IO49NB2F4 IO49PB2F4 IO50NB2F4 IO50PB2F4 IO51NB2F4 IO51PB2F4 IO52NB2F5 IO52PB2F5 IO53NB2F5 IO53PB2F5 IO54NB2F5 IO54PB2F5 IO55NB2F5 IO55PB2F5 IO56NB2F5 IO56PB2F5 G24 G23 G26 F26 F25 E25 J21 J22 H25 G25 K23 J23 J24 H24 K21 K22 K25 J25 L20 L21 K26 J26 L23 L22 L24 K24 M20 M21 L26 L25 Pin Number B23 A23 E21 E20 D23 C23 D25 C25
v2.7
3-37
Axcelerator Family FPGAs
676-Pin FBGA AX500 Function IO57NB2F5 IO57PB2F5 IO58NB2F5 IO58PB2F5 IO59NB2F5 IO59PB2F5 IO60NB2F5 IO60PB2F5 IO61NB2F5 IO61PB2F5 IO62NB2F5 IO62PB2F5 Bank 3 IO63NB3F6 IO63PB3F6 IO64NB3F6 IO64PB3F6 IO65NB3F6 IO65PB3F6 IO66NB3F6 IO66PB3F6 IO67NB3F6 IO67PB3F6 IO68NB3F6 IO68PB3F6 IO69NB3F6 IO69PB3F6 IO70NB3F6 IO70PB3F6 IO71NB3F6 IO71PB3F6 IO72NB3F6 IO72PB3F6 IO73NB3F6 IO73PB3F6 IO74NB3F7 IO74PB3F7 IO75NB3F7 IO75PB3F7 T26 R26 R24 P24 P20 P21 T25 R25 T23 R23 V26 U26 V25 U25 Y25 W25 W24 V24 V23 U23 T21 T20 AA26 Y26 AA24 Y24 Pin Number M23 M22 M26 M25 N22 N23 N24 M24 N20 N21 P25 N25
676-Pin FBGA AX500 Function IO76NB3F7 IO76PB3F7 IO77NB3F7 IO77PB3F7 IO78NB3F7 IO78PB3F7 IO79NB3F7 IO79PB3F7 IO80NB3F7 IO80PB3F7 IO81NB3F7 IO81PB3F7 IO82NB3F7 IO82PB3F7 IO83NB3F7 IO83PB3F7 Bank 4 IO84NB4F8 IO84PB4F8 IO85NB4F8 IO85PB4F8 IO86NB4F8 IO86PB4F8 IO87NB4F8 IO87PB4F8 IO88NB4F8 IO88PB4F8 IO89NB4F8 IO89PB4F8 IO90NB4F8 IO90PB4F8 IO91NB4F8 IO91PB4F8 IO92NB4F8 IO92PB4F8 IO93NB4F8 IO93PB4F8 IO94NB4F9 IO94PB4F9 AB21 AA21 AE23 AE24 AC21 AC22 AF22 AF23 AD22 AD23 AC19 AC20 AE21 AE22 AA17 AA18 AD20 AD21 AF20 AF21 AE19 AE20 Pin Number Y23 W23 V21 U21 AB25 AA25 AC26 AB26 AC24 AB24 AB23 AA23 AA22 Y22 AE26 AD26
676-Pin FBGA AX500 Function IO95NB4F9 IO95PB4F9 IO96NB4F9 IO96PB4F9 IO97NB4F9 IO97PB4F9 IO98NB4F9 IO98PB4F9 IO99NB4F9 IO99PB4F9 IO100NB4F9 IO100PB4F9 IO101NB4F9 IO101PB4F9 IO102NB4F9 IO102PB4F9 IO103NB4F9/CLKEN IO103PB4F9/CLKEP IO104NB4F9/CLKFN IO104PB4F9/CLKFP Bank 5 IO105NB5F10/CLKGN IO105PB5F10/CLKGP IO106NB5F10/CLKHN IO106PB5F10/CLKHP IO107NB5F10 IO107PB5F10 IO108NB5F10 IO108PB5F10 IO109NB5F10 IO109PB5F10 IO110NB5F10 IO110PB5F10 IO111NB5F10 IO111PB5F10 IO112NB5F10 IO112PB5F10 IO113NB5F10 IO113PB5F10 AE12 AE13 AE11 AF11 Y12 AA13 AC12 AB12 AC10 AC11 AF9 AF10 Y11 AA12 AE9 AE10 AC9 AD9 Pin Number AC17 AC18 AD18 AD19 AA16 Y16 AE17 AE18 AC16 AB16 AF17 AF18 AA15 Y15 AC15 AB15 AE16 AF16 AE14 AE15
3 -3 8
v2.7
Axcelerator Family FPGAs
676-Pin FBGA AX500 Function IO114NB5F11 IO114PB5F11 IO115NB5F11 IO115PB5F11 IO116NB5F11 IO116PB5F11 IO117NB5F11 IO117PB5F11 IO118NB5F11 IO118PB5F11 IO119NB5F11 IO119PB5F11 IO120NB5F11 IO120PB5F11 IO121NB5F11 IO121PB5F11 IO122NB5F11 IO122PB5F11 IO123NB5F11 IO123PB5F11 IO124NB5F11 IO124PB5F11 IO125NB5F11 IO125PB5F11 Bank 6 IO126NB6F12 IO126PB6F12 IO127NB6F12 IO127PB6F12 IO128NB6F12 IO128PB6F12 IO129NB6F12 IO129PB6F12 IO130NB6F12 IO130PB6F12 IO131NB6F12 IO131PB6F12 IO132NB6F12 IO132PB6F12 AB3 AC3 AA2 AB2 AC2 AD2 Y1 AA1 Y3 AA3 U6 V6 W2 Y2 Pin Number AF6 AF7 AA10 AB10 AE7 AE8 AD7 AD8 AC7 AC8 AD6 AE6 AE5 AF5 AF4 AE4 AC5 AC6 AD4 AD5 AB6 AB7 AE3 AF3
676-Pin FBGA AX500 Function IO133NB6F12 IO133PB6F12 IO134NB6F12 IO134PB6F12 IO135NB6F12 IO135PB6F12 IO136NB6F13 IO136PB6F13 IO137NB6F13 IO137PB6F13 IO138NB6F13 IO138PB6F13 IO139NB6F13 IO139PB6F13 IO140NB6F13 IO140PB6F13 IO141NB6F13 IO141PB6F13 IO142NB6F13 IO142PB6F13 IO143NB6F13 IO143PB6F13 IO144NB6F13 IO144PB6F13 IO145NB6F13 IO145PB6F13 IO146NB6F13 IO146PB6F13 Bank 7 IO147NB7F14 IO147PB7F14 IO148NB7F14 IO148PB7F14 IO149NB7F14 IO149PB7F14 IO150NB7F14 IO150PB7F14 IO151NB7F14 IO151PB7F14 N6 N7 N5 N4 N2 N3 L1 M1 M2 M3 Pin Number V4 W4 V3 W3 V1 V2 U4 U5 T6 T7 T5 T4 R6 R7 T3 U3 U1 U2 R2 T2 P3 R3 P5 P4 P6 P7 R1 T1
676-Pin FBGA AX500 Function IO152NB7F14 IO152PB7F14 IO153NB7F14 IO153PB7F14 IO154NB7F14 IO154PB7F14 IO155NB7F14 IO155PB7F14 IO156NB7F14 IO156PB7F14 IO157NB7F14 IO157PB7F14 IO158NB7F15 IO158PB7F15 IO159NB7F15 IO159PB7F15 IO160NB7F15 IO160PB7F15 IO161NB7F15 IO161PB7F15 IO162NB7F15 IO162PB7F15 IO163NB7F15 IO163PB7F15 IO164NB7F15 IO164PB7F15 IO165NB7F15 IO165PB7F15 IO166NB7F15 IO166PB7F15 IO167NB7F15 IO167PB7F15 Dedicated I/O GND GND GND GND GND GND A1 A13 A14 A19 A26 A8 Pin Number M5 M4 M7 M6 K2 L2 K3 L3 L5 L4 L6 L7 J1 K1 J4 K4 H2 J2 K6 K5 H3 J3 G2 G1 G4 H4 F3 G3 E2 F2 F5 G5
v2.7
3-39
Axcelerator Family FPGAs
676-Pin FBGA AX500 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AC23 AC4 AD24 AD3 AE2 AE25 AF1 AF13 AF14 AF19 AF26 AF8 B2 B25 B26 C24 C3 G20 G7 H1 H19 H26 H8 J18 J9 K10 K11 K12 K13 K14 K15 K16 K17 L10 L11 L12 L13 L14 L15
676-Pin FBGA AX500 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number L16 L17 M10 M11 M12 M13 M14 M15 M16 M17 N1 N10 N11 N12 N13 N14 N15 N16 N17 N26 P1 P10 P11 P12 P13 P14 P15 P16 P17 P26 R10 R11 R12 R13 R14 R15 R16 R17 T10
676-Pin FBGA AX500 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND/LP NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin Number T11 T12 T13 T14 T15 T16 T17 U10 U11 U12 U13 U14 U15 U16 U17 V18 V9 W1 W19 W26 W8 Y20 Y7 C2 A11 A21 A22 A24 A25 AA11 AA19 AA20 AA4 AA5 AA6 AA7 AA8 AA9 AB1
3 -4 0
v2.7
Axcelerator Family FPGAs
676-Pin FBGA AX500 Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin Number AB11 AB17 AB18 AB19 AB20 AB8 AB9 AC1 AC13 AC14 AC25 AD1 AD11 AD16 AD25 AE1 AF2 AF25 B11 B24 B4 C16 C4 D1 D13 D14 D17 D18 D2 D26 D3 D9 E1 E18 E23 E24 E26 E3 E4
676-Pin FBGA AX500 Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin Number E9 F1 F18 F20 F21 F22 F23 F24 F4 F6 F7 G21 G22 H21 H22 H23 H5 H6 J5 J6 P22 R20 R21 R22 R4 R5 T22 T24 U22 U24 V22 V5 W21 W22 W5 W6 Y21 Y4 Y5
676-Pin FBGA AX500 Function NC PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA Pin Number Y6 E13 B14 Y14 AD14 E5 B3 G6 D4 A2 AB4 AF24 C1 C26 J10 J11 J12 J13 J14 J15 J16 J17 K18 K9 L18 L9 M18 M9 N18 N9 P18 P9 R18 R9 T18 T9 U18 U9 V10
v2.7
3-41
Axcelerator Family FPGAs
676-Pin FBGA AX500 Function VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 VCCIB2 Pin Number V11 V12 V13 V14 V15 V16 V17 A3 AB22 AB5 AD10 AD13 AD17 B1 B17 D24 E14 P2 P23 G10 G8 G9 H10 H11 H12 H13 H9 G17 G18 G19 H14 H15 H16 H17 H18 H20 J19 J20 K19
676-Pin FBGA AX500 Function VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 Pin Number K20 L19 M19 N19 P19 R19 T19 U19 U20 V19 V20 W20 W14 W15 W16 W17 W18 Y17 Y18 Y19 W10 W11 W12 W13 W9 Y10 Y8 Y9 P8 R8 T8 U7 U8 V7 V8 W7 H7 J7 J8
676-Pin FBGA AX500 Function VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number K7 K8 L8 M8 N8 E12 F13 E15 G14 AF15 AA14 AF12 AB13 D12 G13 D15 F14 AD15 AB14 AD12 Y13 E22
3 -4 2
v2.7
Axcelerator Family FPGAs
676-Pin FBGA AX1000 Function Bank 0 IO00NB0F0 IO00PB0F0 IO02NB0F0 IO02PB0F0 IO03NB0F0 IO03PB0F0 IO04NB0F0 IO04PB0F0 IO05NB0F0 IO05PB0F0 IO06NB0F0 IO06PB0F0 IO07NB0F0 IO07PB0F0 IO08NB0F0 IO08PB0F0 IO10NB0F0 IO10PB0F0 IO11NB0F0 IO11PB0F0 IO12NB0F1 IO12PB0F1 IO13NB0F1 IO13PB0F1 IO14NB0F1 IO14PB0F1 IO16NB0F1 IO16PB0F1 IO18NB0F1 IO18PB0F1 IO19NB0F1 IO19PB0F1 IO20NB0F1 IO20PB0F1 IO21NB0F1 IO21PB0F1 IO22NB0F2 IO22PB0F2 B4 C4 E7 E6 D6 D5 B5 C5 A5 A4 F7 F6 B6 C6 C7 D7 F8 E8 A7 A6 C8 D8 B8 B7 D9 E9 F10 F9 B9 C9 A10 A9 D10 E10 B10 C10 F11 G11 Pin Number
676-Pin FBGA AX1000 Function IO24NB0F2 IO24PB0F2 IO26NB0F2 IO26PB0F2 IO28NB0F2 IO28PB0F2 IO30NB0F2/HCLKAN IO30PB0F2/HCLKAP IO31NB0F2/HCLKBN IO31PB0F2/HCLKBP Bank 1 IO32NB1F3/HCLKCN IO32PB1F3/HCLKCP IO33NB1F3/HCLKDN IO33PB1F3/HCLKDP IO35NB1F3 IO35PB1F3 IO36NB1F3 IO36PB1F3 IO38NB1F3 IO38PB1F3 IO40NB1F3 IO40PB1F3 IO41NB1F4 IO41PB1F4 IO42NB1F4 IO42PB1F4 IO44NB1F4 IO44PB1F4 IO45NB1F4 IO45PB1F4 IO46NB1F4 IO46PB1F4 IO48NB1F4 IO48PB1F4 IO49NB1F4 IO49PB1F4 IO50NB1F4 IO50PB1F4 C15 C14 A15 B15 B16 A16 F15 G15 F16 G16 A18 A17 C18 C17 D16 E16 D18 D17 B19 B18 B20 A20 F17 E17 A22 A21 E18 F18 Pin Number D11 E11 C12 C11 F12 G12 A12 B12 C13 B13
676-Pin FBGA AX1000 Function IO51NB1F4 IO51PB1F4 IO52NB1F4 IO52PB1F4 IO54NB1F5 IO54PB1F5 IO55NB1F5 IO55PB1F5 IO56NB1F5 IO56PB1F5 IO57NB1F5 IO57PB1F5 IO58NB1F5 IO58PB1F5 IO59NB1F5 IO59PB1F5 IO60NB1F5 IO60PB1F5 IO62NB1F5 IO62PB1F5 IO63NB1F5 IO63PB1F5 Bank 2 IO64NB2F6 IO64PB2F6 IO65NB2F6 IO65PB2F6 IO66NB2F6 IO66PB2F6 IO67NB2F6 IO67PB2F6 IO68NB2F6 IO68PB2F6 IO69NB2F6 IO69PB2F6 IO70NB2F6 IO70PB2F6 IO71NB2F6 IO71PB2F6 H21 G21 G22 F22 F24 F23 E24 E23 H23 H22 D25 C25 G24 G23 F25 E25 Pin Number D19 C19 D20 C20 B22 B21 D21 C21 F19 E19 B23 A23 D22 C22 B24 A24 E21 E20 D23 C23 F21 F20
v2.7
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Axcelerator Family FPGAs
676-Pin FBGA AX1000 Function IO72NB2F6 IO72PB2F6 IO73NB2F6 IO73PB2F6 IO74NB2F7 IO74PB2F7 IO75NB2F7 IO75PB2F7 IO76NB2F7 IO76PB2F7 IO77NB2F7 IO77PB2F7 IO78NB2F7 IO78PB2F7 IO80NB2F7 IO80PB2F7 IO81NB2F7 IO81PB2F7 IO82NB2F7 IO82PB2F7 IO83NB2F7 IO83PB2F7 IO84NB2F7 IO84PB2F7 IO86NB2F8 IO86PB2F8 IO88NB2F8 IO88PB2F8 IO89NB2F8 IO89PB2F8 IO90NB2F8 IO90PB2F8 IO91NB2F8 IO91PB2F8 IO92NB2F8 IO92PB2F8 IO94NB2F8 IO94PB2F8 IO95NB2F8 Pin Number G26 F26 E26 D26 J21 J22 J24 H24 K23 J23 H25 G25 K25 J25 K21 K22 K26 J26 L24 K24 L23 L22 L20 L21 L26 L25 M23 M22 M26 M25 M20 M21 N24 M24 N22 N23 N20 N21 P25
676-Pin FBGA AX1000 Function IO95PB2F8 Bank 3 IO98NB3F9 IO98PB3F9 IO99NB3F9 IO99PB3F9 IO100NB3F9 IO100PB3F9 IO101NB3F9 IO101PB3F9 IO102NB3F9 IO102PB3F9 IO103NB3F9 IO103PB3F9 IO105NB3F9 IO105PB3F9 IO106NB3F9 IO106PB3F9 IO107NB3F10 IO107PB3F10 IO108NB3F10 IO108PB3F10 IO109NB3F10 IO109PB3F10 IO110NB3F10 IO110PB3F10 IO112NB3F10 IO112PB3F10 IO113NB3F10 IO113PB3F10 IO114NB3F10 IO114PB3F10 IO115NB3F10 IO115PB3F10 IO116NB3F10 IO116PB3F10 IO118NB3F11 IO118PB3F11 IO119NB3F11 P20 P21 R24 P24 R22 P22 T26 R26 R21 R20 T25 R25 V26 U26 T23 R23 U24 T24 U22 T22 V25 U25 T21 T20 V23 U23 Y25 W25 V21 U21 W24 V24 AA26 Y26 AC26 AB26 AB25 Pin Number N25
676-Pin FBGA AX1000 Function IO119PB3F11 IO120NB3F11 IO120PB3F11 IO121NB3F11 IO121PB3F11 IO122NB3F11 IO122PB3F11 IO123NB3F11 IO123PB3F11 IO124NB3F11 IO124PB3F11 IO125NB3F11 IO125PB3F11 IO126NB3F11 IO126PB3F11 IO127NB3F11 IO127PB3F11 IO128NB3F11 IO128PB3F11 Bank 4 IO129NB4F12 IO129PB4F12 IO131NB4F12 IO131PB4F12 IO132NB4F12 IO132PB4F12 IO133NB4F12 IO133PB4F12 IO134NB4F12 IO134PB4F12 IO135NB4F12 IO135PB4F12 IO137NB4F12 IO137PB4F12 IO139NB4F13 IO139PB4F13 IO140NB4F13 IO140PB4F13 IO141NB4F13 AB21 AA21 AD22 AD23 AE23 AE24 AB20 AA20 AC21 AC22 AF22 AF23 AB19 AA19 AC19 AC20 AE21 AE22 AD20 Pin Number AA25 W22 V22 Y23 W23 AA24 Y24 AE26 AD26 Y21 W21 AD25 AC25 AB23 AA23 AC24 AB24 AA22 Y22
3 -4 4
v2.7
Axcelerator Family FPGAs
676-Pin FBGA AX1000 Function IO141PB4F13 IO143NB4F13 IO143PB4F13 IO144NB4F13 IO144PB4F13 IO145NB4F13 IO145PB4F13 IO146NB4F13 IO146PB4F13 IO147NB4F13 IO147PB4F13 IO148NB4F13 IO148PB4F13 IO149NB4F13 IO149PB4F13 IO151NB4F13 IO151PB4F13 IO153NB4F14 IO153PB4F14 IO154NB4F14 IO154PB4F14 IO155NB4F14 IO155PB4F14 IO157NB4F14 IO157PB4F14 IO159NB4F14/CLKEN IO159PB4F14/CLKEP IO160NB4F14/CLKFN IO160PB4F14/CLKFP Bank 5 IO161NB5F15/CLKGN IO161PB5F15/CLKGP IO162NB5F15/CLKHN IO162PB5F15/CLKHP IO163NB5F15 IO163PB5F15 IO165NB5F15 IO165PB5F15 IO167NB5F15 AE12 AE13 AE11 AF11 AC12 AB12 Y12 AA13 Y11 Pin Number AD21 AB17 AB18 AE19 AE20 AC17 AC18 AD18 AD19 AA17 AA18 AF20 AF21 AA16 Y16 AC16 AB16 AE17 AE18 AF17 AF18 AA15 Y15 AC15 AB15 AE16 AF16 AE14 AE15
676-Pin FBGA AX1000 Function IO167PB5F15 IO168NB5F15 IO168PB5F15 IO169NB5F15 IO169PB5F15 IO171NB5F16 IO171PB5F16 IO173NB5F16 IO173PB5F16 IO174NB5F16 IO174PB5F16 IO175NB5F16 IO175PB5F16 IO176NB5F16 IO176PB5F16 IO177NB5F16 IO177PB5F16 IO179NB5F16 IO179PB5F16 IO180NB5F16 IO180PB5F16 IO181NB5F17 IO181PB5F17 IO183NB5F17 IO183PB5F17 IO184NB5F17 IO184PB5F17 IO185NB5F17 IO185PB5F17 IO187NB5F17 IO187PB5F17 IO188NB5F17 IO188PB5F17 IO189NB5F17 IO189PB5F17 IO190NB5F17 IO190PB5F17 IO191NB5F17 IO191PB5F17 Pin Number AA12 AF9 AF10 AB11 AA11 AE9 AE10 AC10 AC11 AE7 AE8 AC9 AD9 AF6 AF7 AA10 AB10 AD7 AD8 AC7 AC8 AA9 AB9 AD6 AE6 AE5 AF5 AA8 AB8 AC5 AC6 AD4 AD5 AB6 AB7 AF4 AE4 AE3 AF3
676-Pin FBGA AX1000 Function IO192NB5F17 IO192PB5F17 Bank 6 IO193NB6F18 IO193PB6F18 IO194NB6F18 IO194PB6F18 IO195NB6F18 IO195PB6F18 IO196NB6F18 IO196PB6F18 IO197NB6F18 IO197PB6F18 IO198NB6F18 IO198PB6F18 IO199NB6F18 IO199PB6F18 IO200NB6F18 IO200PB6F18 IO201NB6F18 IO201PB6F18 IO202NB6F18 IO202PB6F18 IO203NB6F19 IO203PB6F19 IO204NB6F19 IO204PB6F19 IO205NB6F19 IO205PB6F19 IO206NB6F19 IO206PB6F19 IO207NB6F19 IO207PB6F19 IO208NB6F19 IO208PB6F19 IO209NB6F19 IO209PB6F19 IO211NB6F19 IO211PB6F19 Y5 AA5 AB3 AC3 Y4 AA4 AC2 AD2 W6 Y6 AD1 AE1 AA2 AB2 Y3 AA3 V5 W5 AB1 AC1 V4 W4 V3 W3 U6 V6 W2 Y2 U4 U5 Y1 AA1 T6 T7 T3 U3 Pin Number AA6 AA7
v2.7
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Axcelerator Family FPGAs
676-Pin FBGA AX1000 Function IO212NB6F19 IO212PB6F19 IO213NB6F19 IO213PB6F19 IO214NB6F20 IO214PB6F20 IO215NB6F20 IO215PB6F20 IO217NB6F20 IO217PB6F20 IO218NB6F20 IO218PB6F20 IO219NB6F20 IO219PB6F20 IO220NB6F20 IO220PB6F20 IO221NB6F20 IO221PB6F20 IO223NB6F20 IO223PB6F20 Bank 7 IO225NB7F21 IO225PB7F21 IO226NB7F21 IO226PB7F21 IO227NB7F21 IO227PB7F21 IO229NB7F21 IO229PB7F21 IO231NB7F21 IO231PB7F21 IO232NB7F21 IO232PB7F21 IO233NB7F21 IO233PB7F21 IO235NB7F21 IO235PB7F21 IO236NB7F22 IO236PB7F22 N5 N4 N2 N3 N6 N7 M7 M6 M5 M4 L1 M1 M2 M3 K2 L2 L5 L4 Pin Number V1 V2 T5 T4 U1 U2 R6 R7 R5 R4 R2 T2 P3 R3 R1 T1 P6 P7 P5 P4
676-Pin FBGA AX1000 Function IO237NB7F22 IO237PB7F22 IO238NB7F22 IO238PB7F22 IO240NB7F22 IO240PB7F22 IO241NB7F22 IO241PB7F22 IO242NB7F22 IO242PB7F22 IO243NB7F22 IO243PB7F22 IO244NB7F22 IO244PB7F22 IO245NB7F22 IO245PB7F22 IO247NB7F23 IO247PB7F23 IO248NB7F23 IO248PB7F23 IO249NB7F23 IO249PB7F23 IO250NB7F23 IO250PB7F23 IO251NB7F23 IO251PB7F23 IO253NB7F23 IO253PB7F23 IO254NB7F23 IO254PB7F23 IO255NB7F23 IO255PB7F23 IO256NB7F23 IO256PB7F23 IO257NB7F23 IO257PB7F23 Dedicated I/O GND GND A1 A13 Pin Number L6 L7 K3 L3 J1 K1 K6 K5 H2 J2 J4 K4 H3 J3 G2 G1 J6 J5 E1 F1 E2 F2 G4 H4 F3 G3 H6 H5 D2 D1 E4 F4 D3 E3 F5 G5
676-Pin FBGA AX1000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number A14 A19 A26 A8 AC23 AC4 AD24 AD3 AE2 AE25 AF1 AF13 AF14 AF19 AF26 AF8 B2 B25 B26 C24 C3 G20 G7 H1 H19 H26 H8 J18 J9 K10 K11 K12 K13 K14 K15 K16 K17 L10 L11
3 -4 6
v2.7
Axcelerator Family FPGAs
676-Pin FBGA AX1000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number L12 L13 L14 L15 L16 L17 M10 M11 M12 M13 M14 M15 M16 M17 N1 N10 N11 N12 N13 N14 N15 N16 N17 N26 P1 P10 P11 P12 P13 P14 P15 P16 P17 P26 R10 R11 R12 R13 R14
676-Pin FBGA AX1000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND/LP NC NC NC NC NC NC NC PRA PRB PRC PRD Pin Number R15 R16 R17 T10 T11 T12 T13 T14 T15 T16 T17 U10 U11 U12 U13 U14 U15 U16 U17 V18 V9 W1 W19 W26 W8 Y20 Y7 C2 A25 AC13 AC14 AF2 AF25 D13 D14 E13 B14 Y14 AD14
676-Pin FBGA AX1000 Function TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA Pin Number E5 B3 G6 D4 A2 AB4 AF24 C1 C26 J10 J11 J12 J13 J14 J15 J16 J17 K18 K9 L18 L9 M18 M9 N18 N9 P18 P9 R18 R9 T18 T9 U18 U9 V10 V11 V12 V13 V14 V15
v2.7
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Axcelerator Family FPGAs
676-Pin FBGA AX1000 Function VCCA VCCA VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 Pin Number V16 V17 E12 F13 E15 G14 AF15 AA14 AF12 AB13 A11 A3 AB22 AB5 AD10 AD11 AD13 AD16 AD17 B1 B11 B17 C16 D24 E14 P2 P23 G10 G8 G9 H10 H11 H12 H13 H9 G17 G18 G19 H14
676-Pin FBGA AX1000 Function VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 Pin Number H15 H16 H17 H18 H20 J19 J20 K19 K20 L19 M19 N19 P19 R19 T19 U19 U20 V19 V20 W20 W14 W15 W16 W17 W18 Y17 Y18 Y19 W10 W11 W12 W13 W9 Y10 Y8 Y9 P8 R8 T8
676-Pin FBGA AX1000 Function VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number U7 U8 V7 V8 W7 H7 J7 J8 K7 K8 L8 M8 N8 D12 G13 D15 F14 AD15 AB14 AD12 Y13 E22
3 -4 8
v2.7
Axcelerator Family FPGAs
896-Pin FBGA
A1 Ball Pad Corner 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK
Figure 3-7 * 896-Pin FBGA (Bottom View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v2.7
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Axcelerator Family FPGAs
896-Pin FBGA AX1000 Function Bank 0 IO00NB0F0 IO00PB0F0 IO01NB0F0 IO01PB0F0 IO02NB0F0 IO02PB0F0 IO03NB0F0 IO03PB0F0 IO04NB0F0 IO04PB0F0 IO05NB0F0 IO05PB0F0 IO06NB0F0 IO06PB0F0 IO07NB0F0 IO07PB0F0 IO08NB0F0 IO08PB0F0 IO09NB0F0 IO09PB0F0 IO10NB0F0 IO10PB0F0 IO11NB0F0 IO11PB0F0 IO12NB0F1 IO12PB0F1 IO13NB0F1 IO13PB0F1 IO14NB0F1 IO14PB0F1 IO15NB0F1 IO15PB0F1 IO16NB0F1 IO16PB0F1 IO17NB0F1 IO17PB0F1 IO18NB0F1 D6 E6 A5 B5 G9 G8 F8 F7 D7 E7 C7 C6 H9 H8 D8 E8 E9 F9 A7 B7 H10 G10 C9 C8 E10 F10 D10 D9 F11 G11 A10 A9 H12 H11 B11 B10 D11 Pin Number
896-Pin FBGA AX1000 Function IO18PB0F1 IO19NB0F1 IO19PB0F1 IO20NB0F1 IO20PB0F1 IO21NB0F1 IO21PB0F1 IO22NB0F2 IO22PB0F2 IO23NB0F2 IO23PB0F2 IO24NB0F2 IO24PB0F2 IO25NB0F2 IO25PB0F2 IO26NB0F2 IO26PB0F2 IO27NB0F2 IO27PB0F2 IO28NB0F2 IO28PB0F2 IO29NB0F2 IO29PB0F2 IO30NB0F2/HCLKAN IO30PB0F2/HCLKAP IO31NB0F2/HCLKBN IO31PB0F2/HCLKBP Bank 1 IO32NB1F3/HCLKCN IO32PB1F3/HCLKCP IO33NB1F3/HCLKDN IO33PB1F3/HCLKDP IO34NB1F3 IO34PB1F3 IO35NB1F3 IO35PB1F3 IO36NB1F3 IO36PB1F3 E17 E16 C17 D17 A17 B17 D18 C18 H17 J17 Pin Number E11 C12 C11 F12 G12 D12 E12 H13 J13 A12 A11 F13 G13 B13 B12 E14 E13 B14 A14 H14 J14 B15 A15 C14 D14 E15 D15
896-Pin FBGA AX1000 Function IO37NB1F3 IO37PB1F3 IO38NB1F3 IO38PB1F3 IO39NB1F3 IO39PB1F3 IO40NB1F3 IO40PB1F3 IO41NB1F4 IO41PB1F4 IO42NB1F4 IO42PB1F4 IO43NB1F4 IO43PB1F4 IO44NB1F4 IO44PB1F4 IO45NB1F4 IO45PB1F4 IO46NB1F4 IO46PB1F4 IO47NB1F4 IO47PB1F4 IO48NB1F4 IO48PB1F4 IO49NB1F4 IO49PB1F4 IO50NB1F4 IO50PB1F4 IO51NB1F4 IO51PB1F4 IO52NB1F4 IO52PB1F4 IO53NB1F4 IO53PB1F4 IO54NB1F5 IO54PB1F5 IO55NB1F5 IO55PB1F5 Pin Number B19 A19 H18 J18 B20 A20 C20 C19 E20 E19 F18 G18 A22 A21 F20 F19 D21 D20 D22 C22 A25 A24 H19 G19 C24 C23 G20 H20 F21 E21 F22 E22 B25 B24 D24 D23 F23 E23
3 -5 0
v2.7
Axcelerator Family FPGAs
896-Pin FBGA AX1000 Function IO56NB1F5 IO56PB1F5 IO57NB1F5 IO57PB1F5 IO58NB1F5 IO58PB1F5 IO59NB1F5 IO59PB1F5 IO60NB1F5 IO60PB1F5 IO61NB1F5 IO61PB1F5 IO62NB1F5 IO62PB1F5 IO63NB1F5 IO63PB1F5 Bank 2 IO64NB2F6 IO64PB2F6 IO65NB2F6 IO65PB2F6 IO66NB2F6 IO66PB2F6 IO67NB2F6 IO67PB2F6 IO68NB2F6 IO68PB2F6 IO69NB2F6 IO69PB2F6 IO70NB2F6 IO70PB2F6 IO71NB2F6 IO71PB2F6 IO72NB2F6 IO72PB2F6 IO73NB2F6 IO73PB2F6 IO74NB2F7 K23 J23 J24 H24 H26 H25 G26 G25 K25 K24 F27 E27 J26 J25 H27 G27 J28 H28 G28 F28 L23 Pin Number H21 G21 D25 C25 F24 E24 D26 C26 G23 G22 B27 A27 F25 E25 H23 H22
896-Pin FBGA AX1000 Function IO74PB2F7 IO75NB2F7 IO75PB2F7 IO76NB2F7 IO76PB2F7 IO77NB2F7 IO77PB2F7 IO78NB2F7 IO78PB2F7 IO79NB2F7 IO79PB2F7 IO80NB2F7 IO80PB2F7 IO81NB2F7 IO81PB2F7 IO82NB2F7 IO82PB2F7 IO83NB2F7 IO83PB2F7 IO84NB2F7 IO84PB2F7 IO85NB2F8 IO85PB2F8 IO86NB2F8 IO86PB2F8 IO87NB2F8 IO87PB2F8 IO88NB2F8 IO88PB2F8 IO89NB2F8 IO89PB2F8 IO90NB2F8 IO90PB2F8 IO91NB2F8 IO91PB2F8 IO92NB2F8 IO92PB2F8 IO93NB2F8 Pin Number L24 L26 K26 M25 L25 K27 J27 M27 L27 K30 K29 M23 M24 M28 L28 N26 M26 N25 N24 N22 N23 M29 L29 N28 N27 P29 P30 P25 P24 P28 P27 P22 P23 R26 P26 R24 R25 R29
896-Pin FBGA AX1000 Function IO93PB2F8 IO94NB2F8 IO94PB2F8 IO95NB2F8 IO95PB2F8 Bank 3 IO96NB3F9 IO96PB3F9 IO97NB3F9 IO97PB3F9 IO98NB3F9 IO98PB3F9 IO99NB3F9 IO99PB3F9 IO100NB3F9 IO100PB3F9 IO101NB3F9 IO101PB3F9 IO102NB3F9 IO102PB3F9 IO103NB3F9 IO103PB3F9 IO104NB3F9 IO104PB3F9 IO105NB3F9 IO105PB3F9 IO106NB3F9 IO106PB3F9 IO107NB3F10 IO107PB3F10 IO108NB3F10 IO108PB3F10 IO109NB3F10 IO109PB3F10 IO110NB3F10 IO110PB3F10 IO111NB3F10 IO111PB3F10 T29 T30 U29 U30 T22 T23 U26 T26 U24 T24 V28 U28 U23 U22 V27 U27 W29 V29 Y28 W28 V25 U25 W26 V26 W24 V24 Y27 W27 V23 V22 AA29 Y29 Pin Number R30 R22 R23 T27 R27
v2.7
3-51
Axcelerator Family FPGAs
896-Pin FBGA AX1000 Function IO112NB3F10 IO112PB3F10 IO113NB3F10 IO113PB3F10 IO114NB3F10 IO114PB3F10 IO115NB3F10 IO115PB3F10 IO116NB3F10 IO116PB3F10 IO117NB3F10 IO117PB3F10 IO118NB3F11 IO118PB3F11 IO119NB3F11 IO119PB3F11 IO120NB3F11 IO120PB3F11 IO121NB3F11 IO121PB3F11 IO122NB3F11 IO122PB3F11 IO123NB3F11 IO123PB3F11 IO124NB3F11 IO124PB3F11 IO125NB3F11 IO125PB3F11 IO126NB3F11 IO126PB3F11 IO127NB3F11 IO127PB3F11 IO128NB3F11 IO128PB3F11 Bank 4 IO129NB4F12 IO129PB4F12 IO130NB4F12 AD23 AC23 AK26 Pin Number Y25 W25 AB27 AA27 Y23 W23 AA26 Y26 AC28 AB28 AE29 AD29 AE28 AD28 AD27 AC27 AA24 Y24 AB25 AA25 AC26 AB26 AG28 AF28 AB23 AA23 AF27 AE27 AD25 AC25 AE26 AD26 AC24 AB24
896-Pin FBGA AX1000 Function IO130PB4F12 IO131NB4F12 IO131PB4F12 IO132NB4F12 IO132PB4F12 IO133NB4F12 IO133PB4F12 IO134NB4F12 IO134PB4F12 IO135NB4F12 IO135PB4F12 IO136NB4F12 IO136PB4F12 IO137NB4F12 IO137PB4F12 IO138NB4F12 IO138PB4F12 IO139NB4F13 IO139PB4F13 IO140NB4F13 IO140PB4F13 IO141NB4F13 IO141PB4F13 IO142NB4F13 IO142PB4F13 IO143NB4F13 IO143PB4F13 IO144NB4F13 IO144PB4F13 IO145NB4F13 IO145PB4F13 IO146NB4F13 IO146PB4F13 IO147NB4F13 IO147PB4F13 IO148NB4F13 IO148PB4F13 IO149NB4F13 Pin Number AK27 AF24 AF25 AG25 AG26 AD22 AC22 AE23 AE24 AH24 AH25 AJ25 AJ26 AD21 AC21 AK24 AK25 AE21 AE22 AG23 AG24 AF22 AF23 AJ23 AJ24 AD19 AD20 AG21 AG22 AE19 AE20 AF20 AF21 AC19 AC20 AH22 AH23 AC18
896-Pin FBGA AX1000 Function IO149PB4F13 IO150NB4F13 IO150PB4F13 IO151NB4F13 IO151PB4F13 IO152NB4F14 IO152PB4F14 IO153NB4F14 IO153PB4F14 IO154NB4F14 IO154PB4F14 IO155NB4F14 IO155PB4F14 IO156NB4F14 IO156PB4F14 IO157NB4F14 IO157PB4F14 IO158NB4F14 IO158PB4F14 IO159NB4F14/CLKEN IO159PB4F14/CLKEP IO160NB4F14/CLKFN IO160PB4F14/CLKFP Bank 5 IO161NB5F15/CLKGN IO161PB5F15/CLKGP IO162NB5F15/CLKHN IO162PB5F15/CLKHP IO163NB5F15 IO163PB5F15 IO164NB5F15 IO164PB5F15 IO165NB5F15 IO165PB5F15 IO166NB5F15 IO166PB5F15 IO167NB5F15 IO167PB5F15 AG14 AG15 AG13 AH13 AE14 AD14 AJ12 AJ13 AB14 AC15 AK11 AK12 AB13 AC14 Pin Number AB18 AK21 AJ21 AE18 AD18 AJ20 AK20 AG19 AG20 AH19 AH20 AC17 AB17 AK19 AJ19 AE17 AD17 AJ17 AJ18 AG18 AH18 AG16 AG17
3 -5 2
v2.7
Axcelerator Family FPGAs
896-Pin FBGA AX1000 Function IO168NB5F15 IO168PB5F15 IO169NB5F15 IO169PB5F15 IO170NB5F15 IO170PB5F15 IO171NB5F16 IO171PB5F16 IO172NB5F16 IO172PB5F16 IO173NB5F16 IO173PB5F16 IO174NB5F16 IO174PB5F16 IO175NB5F16 IO175PB5F16 IO176NB5F16 IO176PB5F16 IO177NB5F16 IO177PB5F16 IO178NB5F16 IO178PB5F16 IO179NB5F16 IO179PB5F16 IO180NB5F16 IO180PB5F16 IO181NB5F17 IO181PB5F17 IO182NB5F17 IO182PB5F17 IO183NB5F17 IO183PB5F17 IO184NB5F17 IO184PB5F17 IO185NB5F17 IO185PB5F17 IO186NB5F17 IO186PB5F17 Pin Number AH11 AH12 AD13 AC13 AJ10 AJ11 AG11 AG12 AK9 AK10 AE12 AE13 AG9 AG10 AE11 AF11 AH8 AH9 AC12 AD12 AJ7 AJ8 AF9 AF10 AE9 AE10 AC11 AD11 AK6 AK7 AF8 AG8 AG7 AH7 AC10 AD10 AJ5 AJ6
896-Pin FBGA AX1000 Function IO187NB5F17 IO187PB5F17 IO188NB5F17 IO188PB5F17 IO189NB5F17 IO189PB5F17 IO190NB5F17 IO190PB5F17 IO191NB5F17 IO191PB5F17 IO192NB5F17 IO192PB5F17 Bank 6 IO193NB6F18 IO193PB6F18 IO194NB6F18 IO194PB6F18 IO195NB6F18 IO195PB6F18 IO196NB6F18 IO196PB6F18 IO197NB6F18 IO197PB6F18 IO198NB6F18 IO198PB6F18 IO199NB6F18 IO199PB6F18 IO200NB6F18 IO200PB6F18 IO201NB6F18 IO201PB6F18 IO202NB6F18 IO202PB6F18 IO203NB6F19 IO203PB6F19 IO204NB6F19 IO204PB6F19 IO205NB6F19 AB7 AC7 AD5 AE5 AB6 AC6 AE4 AF4 AA8 AB8 AF3 AG3 AC4 AD4 AB5 AC5 Y7 AA7 AD3 AE3 Y6 AA6 Y5 AA5 W8 Pin Number AE7 AE8 AF6 AF7 AD8 AD9 AH6 AG6 AG5 AH5 AC8 AC9
896-Pin FBGA AX1000 Function IO205PB6F19 IO206NB6F19 IO206PB6F19 IO207NB6F19 IO207PB6F19 IO208NB6F19 IO208PB6F19 IO209NB6F19 IO209PB6F19 IO210NB6F19 IO210PB6F19 IO211NB6F19 IO211PB6F19 IO212NB6F19 IO212PB6F19 IO213NB6F19 IO213PB6F19 IO214NB6F20 IO214PB6F20 IO215NB6F20 IO215PB6F20 IO216NB6F20 IO216PB6F20 IO217NB6F20 IO217PB6F20 IO218NB6F20 IO218PB6F20 IO219NB6F20 IO219PB6F20 IO220NB6F20 IO220PB6F20 IO221NB6F20 IO221PB6F20 IO222NB6F20 IO222PB6F20 IO223NB6F20 IO223PB6F20 IO224NB6F20 Pin Number Y8 AA4 AB4 W6 W7 AB3 AC3 V8 V9 AA2 AA1 V5 W5 Y3 Y4 V7 V6 W3 W4 U8 U9 W1 W2 U7 U6 U4 V4 T5 U5 U3 V3 T8 T9 U2 V2 T7 T6 R2
v2.7
3-53
Axcelerator Family FPGAs
896-Pin FBGA AX1000 Function IO224PB6F20 Bank 7 IO225NB7F21 IO225PB7F21 IO226NB7F21 IO226PB7F21 IO227NB7F21 IO227PB7F21 IO228NB7F21 IO228PB7F21 IO229NB7F21 IO229PB7F21 IO230NB7F21 IO230PB7F21 IO231NB7F21 IO231PB7F21 IO232NB7F21 IO232PB7F21 IO233NB7F21 IO233PB7F21 IO234NB7F21 IO234PB7F21 IO235NB7F21 IO235PB7F21 IO236NB7F22 IO236PB7F22 IO237NB7F22 IO237PB7F22 IO238NB7F22 IO238PB7F22 IO239NB7F22 IO239PB7F22 IO240NB7F22 IO240PB7F22 IO241NB7F22 IO241PB7F22 IO242NB7F22 IO242PB7F22 R7 R6 R4 R5 R8 R9 P1 R1 P9 P8 N2 P2 P7 P6 N3 P3 P4 P5 L1 M1 M4 N4 N7 N6 N8 N9 M5 N5 L2 M2 L3 M3 M8 M7 K4 L4 Pin Number T2
896-Pin FBGA AX1000 Function IO243NB7F22 IO243PB7F22 IO244NB7F22 IO244PB7F22 IO245NB7F22 IO245PB7F22 IO246NB7F22 IO246PB7F22 IO247NB7F23 IO247PB7F23 IO248NB7F23 IO248PB7F23 IO249NB7F23 IO249PB7F23 IO250NB7F23 IO250PB7F23 IO251NB7F23 IO251PB7F23 IO252NB7F23 IO252PB7F23 IO253NB7F23 IO253PB7F23 IO254NB7F23 IO254PB7F23 IO255NB7F23 IO255PB7F23 IO256NB7F23 IO256PB7F23 IO257NB7F23 IO257PB7F23 Dedicated I/O GND GND GND GND GND GND GND A13 A18 A2 A23 A29 A8 AA10 Pin Number L6 M6 K5 L5 J4 J3 G2 H2 L8 L7 G3 H3 G4 H4 J6 K6 H5 J5 F2 F1 K8 K7 F4 F3 G6 H6 F5 G5 H7 J7
896-Pin FBGA AX1000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AA21 AA28 AA3 AB2 AB22 AB29 AB9 AC1 AC30 AE25 AE6 AF26 AF5 AG27 AG4 AH10 AH15 AH16 AH21 AH28 AH3 AJ1 AJ2 AJ22 AJ29 AJ30 AJ9 AK13 AK18 AK2 AK23 AK29 AK8 B1 B2 B22 B29 B30
3 -5 4
v2.7
Axcelerator Family FPGAs
896-Pin FBGA AX1000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number B9 C10 C15 C16 C21 C28 C3 D27 D28 D4 E26 E5 H1 H30 J2 J22 J29 J9 K10 K21 K28 K3 L11 L20 M12 M13 M14 M15 M16 M17 M18 M19 N1 N12 N13 N14 N15 N16
896-Pin FBGA AX1000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number N17 N18 N19 N30 P12 P13 P14 P15 P16 P17 P18 P19 R12 R13 R14 R15 R16 R17 R18 R19 R28 R3 T12 T13 T14 T15 T16 T17 T18 T19 T28 T3 U12 U13 U14 U15 U16 U17
896-Pin FBGA AX1000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND/LP NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin Number U18 U19 V1 V12 V13 V14 V15 V16 V17 V18 V19 V30 W12 W13 W14 W15 W16 W17 W18 W19 Y11 Y20 E4 A16 A26 A4 A6 AA30 AB1 AB30 AC2 AC29 AD1 AD2 AD30 AE1 AE15 AE16
v2.7
3-55
Axcelerator Family FPGAs
896-Pin FBGA AX1000 Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin Number AE2 AE30 AF1 AF2 AF29 AF30 AG1 AG2 AG29 AG30 AH27 AH4 AJ14 AJ15 AJ16 AJ27 AJ4 AK14 AK15 AK16 AK17 AK22 AK4 AK5 B16 B18 B21 B23 B26 B4 B6 B8 C27 D1 D2 D29 D30 E1
896-Pin FBGA AX1000 Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA Pin Number E2 E29 E30 F15 F16 F29 F30 G1 G29 G30 H29 J1 J30 K1 K2 L30 M30 N29 T1 U1 W30 Y1 Y2 Y30 G15 D16 AB16 AF16 G7 D5 J8 F6 C4 AD6 AH26 E28 E3 L12
896-Pin FBGA AX1000 Function VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG Pin Number L13 L14 L15 L16 L17 L18 L19 M11 M20 N11 N20 P11 P20 R11 R20 T11 T20 U11 U20 V11 V20 W11 W20 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 G14 H15 G17 J16 AH17 AC16 AH14
3 -5 6
v2.7
Axcelerator Family FPGAs
896-Pin FBGA AX1000 Function VCCPLH VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 Pin Number AD15 AD24 AD7 AF12 AF13 AF15 AF18 AF19 C13 C5 D13 D19 D3 E18 F26 G16 T25 T4 A3 B3 J10 J11 J12 K11 K12 K13 K14 K15 A28 B28 J19 J20 J21 K16 K17 K18 K19 K20
896-Pin FBGA AX1000 Function VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 Pin Number C29 C30 K22 L21 L22 M21 M22 N21 P21 R21 AA22 AH29 AH30 T21 U21 V21 W21 W22 Y21 Y22 AA16 AA17 AA18 AA19 AA20 AB19 AB20 AB21 AJ28 AK28 AA11 AA12 AA13 AA14 AA15 AB10 AB11 AB12
896-Pin FBGA AX1000 Function VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number AJ3 AK3 AA9 AH1 AH2 T10 U10 V10 W10 W9 Y10 Y9 C1 C2 K9 L10 L9 M10 M9 N10 P10 R10 F14 J15 F17 H16 AF17 AD16 AF14 AB15 G24
v2.7
3-57
Axcelerator Family FPGAs
896-Pin FBGA AX2000 Function Bank 0 IO00NB0F0 IO00PB0F0 IO01NB0F0 IO01PB0F0 IO02NB0F0 IO02PB0F0 IO04NB0F0 IO04PB0F0 IO05NB0F0 IO05PB0F0 IO06NB0F0 IO06PB0F0 IO07NB0F0 IO07PB0F0 IO08NB0F0 IO08PB0F0 IO09NB0F0 IO09PB0F0 IO10NB0F0 IO10PB0F0 IO11NB0F0 IO11PB0F0 IO12NB0F1 IO12PB0F1 IO13NB0F1 IO13PB0F1 IO15NB0F1 IO15PB0F1 IO16NB0F1 IO16PB0F1 IO17NB0F1 IO17PB0F1 IO18NB0F1 B4 A4 F8 F7 D6 E6 A5 B5 H8 G8 D7 E7 D8 E8 C7 C6 G9 H9 A6 B6 H10 G10 E9 F9 E10 F10 F11 G11 A7 B7 D10 D9 C9 Pin Number
896-Pin FBGA AX2000 Function IO18PB0F1 IO19NB0F1 IO19PB0F1 IO20PB0F1 IO21NB0F1 IO21PB0F1 IO23NB0F2 IO23PB0F2 IO25NB0F2 IO25PB0F2 IO26NB0F2 IO26PB0F2 IO27NB0F2 IO27PB0F2 IO28NB0F2 IO28PB0F2 IO30NB0F2 IO30PB0F2 IO31NB0F2 IO31PB0F2 IO33NB0F2 IO33PB0F2 IO34NB0F3 IO34PB0F3 IO37NB0F3 IO37PB0F3 IO38NB0F3 IO38PB0F3 IO39NB0F3 IO39PB0F3 IO40NB0F3 IO40PB0F3 IO41NB0F3/HCLKAN IO41PB0F3/HCLKAP Pin Number C8 D11 E11 B8 H12 H11 A10 A9 F12 G12 B11 B10 D12 E12 C12 C11 A12 A11 F13 G13 H13 J13 B13 B12 E14 E13 B14 A14 H14 J14 B15 A15 C14 D14
896-Pin FBGA AX2000 Function IO42NB0F3/HCLKBN IO42PB0F3/HCLKBP Bank 1 IO43NB1F4/HCLKCN IO43PB1F4/HCLKCP IO44NB1F4/HCLKDN IO44PB1F4/HCLKDP IO45NB1F4 IO45PB1F4 IO47NB1F4 IO47PB1F4 IO48NB1F4 IO48PB1F4 IO49NB1F4 IO49PB1F4 IO51NB1F4 IO51PB1F4 IO52NB1F4 IO53NB1F4 IO53PB1F4 IO55NB1F5 IO55PB1F5 IO56NB1F5 IO56PB1F5 IO57NB1F5 IO57PB1F5 IO58NB1F5 IO58PB1F5 IO59NB1F5 IO59PB1F5 IO61NB1F5 IO61PB1F5 IO62NB1F5 IO62PB1F5 E17 E16 C17 D17 A16 B16 H17 J17 A17 B17 H18 J18 F18 G18 B18 D18 C18 H19 G19 B19 A19 E20 E19 C20 C19 B20 A20 F20 F19 A22 A21 Pin Number E15 D15
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
3 -5 8
v2.7
Axcelerator Family FPGAs
896-Pin FBGA AX2000 Function IO63NB1F5 IO63PB1F5 IO65NB1F6 IO65PB1F6 IO66NB1F6 IO66PB1F6 IO67NB1F6 IO67PB1F6 IO68NB1F6 IO68PB1F6 IO69NB1F6 IO69PB1F6 IO70NB1F6 IO70PB1F6 IO71NB1F6 IO71PB1F6 IO73NB1F6 IO73PB1F6 IO74NB1F6 IO74PB1F6 IO75NB1F6 IO75PB1F6 IO76NB1F7 IO76PB1F7 IO78NB1F7 IO78PB1F7 IO79NB1F7 IO79PB1F7 IO80NB1F7 IO80PB1F7 IO81NB1F7 IO81PB1F7 IO82NB1F7 IO82PB1F7 Pin Number D21 D20 G20 H20 B23 B21 H21 G21 D22 C22 A25 A24 F22 E22 F21 E21 C24 C23 D24 D23 H23 H22 B25 B24 B26 A26 F23 E23 D25 C25 G23 G22 B27 A27
896-Pin FBGA AX2000 Function IO83NB1F7 IO83PB1F7 IO84NB1F7 IO84PB1F7 IO85NB1F7 IO85PB1F7 Bank 2 IO86NB2F8 IO86PB2F8 IO87NB2F8 IO87PB2F8 IO88NB2F8 IO88PB2F8 IO89NB2F8 IO89PB2F8 IO90NB2F8 IO90PB2F8 IO91NB2F8 IO91PB2F8 IO92NB2F8 IO92PB2F8 IO93NB2F8 IO93PB2F8 IO94NB2F8 IO94PB2F8 IO95NB2F8 IO95PB2F8 IO96NB2F9 IO96PB2F9 IO97NB2F9 IO97PB2F9 IO98NB2F9 IO98PB2F9 IO99NB2F9 G26 G25 K23 J23 J24 H24 E29 D29 F27 E27 H26 H25 G28 F28 J26 J25 H27 G27 H29 G29 G30 F30 K25 K24 J28 H28 L23 Pin Number F24 E24 D26 C26 F25 E25
896-Pin FBGA AX2000 Function IO99PB2F9 IO100NB2F9 IO100PB2F9 IO101PB2F9 IO102NB2F9 IO102PB2F9 IO103NB2F9 IO103PB2F9 IO104NB2F9 IO105NB2F9 IO105PB2F9 IO106NB2F9 IO106PB2F9 IO107NB2F10 IO107PB2F10 IO109NB2F10 IO109PB2F10 IO110NB2F10 IO110PB2F10 IO111NB2F10 IO111PB2F10 IO112NB2F10 IO112PB2F10 IO113NB2F10 IO113PB2F10 IO114NB2F10 IO114PB2F10 IO115NB2F10 IO115PB2F10 IO117NB2F10 IO117PB2F10 IO118NB2F11 IO119NB2F11 IO119PB2F11 Pin Number L24 K27 J27 J30 E30 D30 L26 K26 F29 M25 L25 K30 K29 M23 M24 M27 L27 M28 L28 N22 N23 M29 L29 N26 M26 M30 L30 N28 N27 N25 N24 N29 P22 P23
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
v2.7
3-59
Axcelerator Family FPGAs
896-Pin FBGA AX2000 Function IO121NB2F11 IO121PB2F11 IO122NB2F11 IO122PB2F11 IO123NB2F11 IO123PB2F11 IO124NB2F11 IO124PB2F11 IO125NB2F11 IO125PB2F11 IO127NB2F11 IO127PB2F11 IO128NB2F11 IO128PB2F11 Bank 3 IO129NB3F12 IO129PB3F12 IO130NB3F12 IO130PB3F12 IO131NB3F12 IO131PB3F12 IO132NB3F12 IO132PB3F12 IO133NB3F12 IO133PB3F12 IO135NB3F12 IO135PB3F12 IO136NB3F12 IO136PB3F12 IO137NB3F12 IO137PB3F12 IO138NB3F12 IO138PB3F12 IO139NB3F13 T27 R27 T29 T30 T22 T23 U26 T26 U24 T24 U23 U22 U29 U30 V28 U28 V27 U27 V25 Pin Number P25 P24 P28 P27 R26 P26 P29 P30 R22 R23 R24 R25 R29 R30
896-Pin FBGA AX2000 Function IO139PB3F13 IO141NB3F13 IO141PB3F13 IO142NB3F13 IO142PB3F13 IO143NB3F13 IO143PB3F13 IO145NB3F13 IO145PB3F13 IO146NB3F13 IO146PB3F13 IO147NB3F13 IO147PB3F13 IO148NB3F13 IO148PB3F13 IO149NB3F13 IO149PB3F13 IO150NB3F14 IO150PB3F14 IO151NB3F14 IO152NB3F14 IO152PB3F14 IO153NB3F14 IO153PB3F14 IO154NB3F14 IO154PB3F14 IO155NB3F14 IO155PB3F14 IO156NB3F14 IO156PB3F14 IO157NB3F14 IO157PB3F14 IO158NB3F14 IO158PB3F14 Pin Number U25 V23 V22 W29 V29 W26 V26 W24 V24 W27 W28 Y28 Y27 Y30 W30 Y25 W25 AA29 Y29 AC29 AA26 Y26 Y23 W23 AB30 AA30 AB27 AA27 AC28 AB28 AA24 Y24 AF29 AF30
896-Pin FBGA AX2000 Function IO159NB3F14 IO159PB3F14 IO160NB3F14 IO160PB3F14 IO161NB3F15 IO161PB3F15 IO162NB3F15 IO162PB3F15 IO163NB3F15 IO163PB3F15 IO164NB3F15 IO164PB3F15 IO165NB3F15 IO165PB3F15 IO166NB3F15 IO166PB3F15 IO167NB3F15 IO167PB3F15 IO168NB3F15 IO168PB3F15 IO169NB3F15 IO169PB3F15 IO170NB3F15 IO170PB3F15 Bank 4 IO171NB4F16 IO171PB4F16 IO172NB4F16 IO172PB4F16 IO173NB4F16 IO173PB4F16 IO174NB4F16 IO174PB4F16 IO175NB4F16 AG29 AG30 AF24 AF25 AG25 AG26 AJ25 AJ26 AK26 Pin Number AB25 AA25 AE30 AD30 AE29 AD29 AD27 AC27 AC26 AB26 AE28 AD28 AC24 AB24 AG28 AF28 AE26 AD26 AD25 AC25 AF27 AE27 AB23 AA23
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
3 -6 0
v2.7
Axcelerator Family FPGAs
896-Pin FBGA AX2000 Function IO175PB4F16 IO176NB4F16 IO176PB4F16 IO177NB4F16 IO177PB4F16 IO178NB4F16 IO178PB4F16 IO179PB4F16 IO180NB4F16 IO180PB4F16 IO181NB4F17 IO181PB4F17 IO182NB4F17 IO182PB4F17 IO183NB4F17 IO183PB4F17 IO184NB4F17 IO184PB4F17 IO185NB4F17 IO185PB4F17 IO187NB4F17 IO187PB4F17 IO188NB4F17 IO188PB4F17 IO189PB4F17 IO190NB4F17 IO190PB4F17 IO191NB4F17 IO191PB4F17 IO192NB4F17 IO192PB4F17 IO195NB4F18 IO195PB4F18 IO196NB4F18 Pin Number AK27 AE23 AE24 AH24 AH25 AD23 AC23 AJ27 AG23 AG24 AK24 AK25 AD22 AC22 AF22 AF23 AE21 AE22 AJ23 AJ24 AH22 AH23 AD21 AC21 AK22 AF20 AF21 AG21 AG22 AE19 AE20 AK21 AJ21 AD19
896-Pin FBGA AX2000 Function IO196PB4F18 IO197NB4F18 IO197PB4F18 IO198NB4F18 IO198PB4F18 IO199NB4F18 IO199PB4F18 IO200NB4F18 IO200PB4F18 IO201NB4F18 IO201PB4F18 IO202NB4F18 IO202PB4F18 IO206NB4F19 IO206PB4F19 IO207NB4F19 IO207PB4F19 IO208NB4F19 IO208PB4F19 IO209NB4F19 IO210NB4F19 IO210PB4F19 IO211NB4F19 IO211PB4F19 IO212NB4F19/CLKEN IO212PB4F19/CLKEP IO213NB4F19/CLKFN IO213PB4F19/CLKFP Bank 5 IO214NB5F20/CLKGN IO214PB5F20/CLKGP IO215NB5F20/CLKHN IO215PB5F20/CLKHP IO216NB5F20 AG14 AG15 AG13 AH13 AB14 Pin Number AD20 AJ20 AK20 AC19 AC20 AG19 AG20 AH19 AH20 AK19 AJ19 AC18 AB18 AE18 AD18 AJ17 AJ18 AE17 AD17 AK17 AC17 AB17 AJ16 AK16 AG18 AH18 AG16 AG17
896-Pin FBGA AX2000 Function IO216PB5F20 IO217NB5F20 IO217PB5F20 IO218NB5F20 IO218PB5F20 IO219NB5F20 IO219PB5F20 IO222NB5F20 IO222PB5F20 IO223NB5F21 IO223PB5F21 IO225NB5F21 IO225PB5F21 IO226NB5F21 IO226PB5F21 IO227NB5F21 IO227PB5F21 IO228NB5F21 IO228PB5F21 IO229NB5F21 IO229PB5F21 IO230NB5F21 IO230PB5F21 IO232NB5F21 IO232PB5F21 IO233NB5F21 IO233PB5F21 IO234NB5F21 IO234PB5F21 IO236NB5F22 IO236PB5F22 IO237NB5F22 IO237PB5F22 IO238NB5F22 Pin Number AC15 AK15 AJ15 AE14 AD14 AK14 AJ14 AB13 AC14 AJ12 AJ13 AH11 AH12 AC13 AD13 AE12 AE13 AG11 AG12 AK11 AK12 AC12 AD12 AE11 AF11 AJ10 AJ11 AC11 AD11 AK9 AK10 AG9 AG10 AF9
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
v2.7
3-61
Axcelerator Family FPGAs
896-Pin FBGA AX2000 Function IO238PB5F22 IO239NB5F22 IO239PB5F22 IO240NB5F22 IO240PB5F22 IO242NB5F22 IO242PB5F22 IO243NB5F22 IO243PB5F22 IO244NB5F22 IO244PB5F22 IO245NB5F23 IO245PB5F23 IO246NB5F23 IO246PB5F23 IO247NB5F23 IO247PB5F23 IO248NB5F23 IO249NB5F23 IO249PB5F23 IO250NB5F23 IO250PB5F23 IO251NB5F23 IO251PB5F23 IO252NB5F23 IO252PB5F23 IO253NB5F23 IO253PB5F23 IO254NB5F23 IO254PB5F23 IO255NB5F23 IO255PB5F23 IO256NB5F23 IO256PB5F23 Pin Number AF10 AH8 AH9 AC10 AD10 AE9 AE10 AJ7 AJ8 AK6 AK7 AF8 AG8 AD8 AD9 AG7 AH7 AK5 AJ5 AJ6 AC8 AC9 AH6 AG6 AF6 AF7 AG2 AG1 AE7 AE8 AG5 AH5 AJ4 AK4
896-Pin FBGA AX2000 Function Bank 6 IO257NB6F24 IO257PB6F24 IO258NB6F24 IO258PB6F24 IO259NB6F24 IO259PB6F24 IO260NB6F24 IO260PB6F24 IO261NB6F24 IO261PB6F24 IO262NB6F24 IO262PB6F24 IO263NB6F24 IO263PB6F24 IO264NB6F24 IO264PB6F24 IO265NB6F24 IO265PB6F24 IO266NB6F24 IO266PB6F24 IO267NB6F25 IO267PB6F25 IO268NB6F25 IO268PB6F25 IO269NB6F25 IO269PB6F25 IO270NB6F25 IO270PB6F25 IO271NB6F25 IO271PB6F25 IO272NB6F25 IO272PB6F25 IO273NB6F25 AE4 AF4 AB7 AC7 AD5 AE5 AF1 AF2 AF3 AG3 AC4 AD4 AD3 AE3 AB6 AC6 AD1 AE1 AA8 AB8 AB5 AC5 AB3 AC3 AC2 AD2 Y7 AA7 AA4 AB4 Y6 AA6 AB1* Pin Number
896-Pin FBGA AX2000 Function IO273PB6F25 IO274NB6F25 IO274PB6F25 IO275NB6F25 IO275PB6F25 IO277NB6F25 IO277PB6F25 IO278NB6F26 IO278PB6F26 IO279NB6F26 IO279PB6F26 IO280NB6F26 IO280PB6F26 IO281NB6F26 IO281PB6F26 IO282NB6F26 IO282PB6F26 IO284NB6F26 IO284PB6F26 IO285NB6F26 IO285PB6F26 IO286NB6F26 IO286PB6F26 IO287NB6F26 IO287PB6F26 IO288NB6F26 IO288PB6F26 IO290NB6F27 IO290PB6F27 IO291NB6F27 IO291PB6F27 IO292NB6F27 IO292PB6F27 IO293NB6F27 Pin Number AE2* W8 Y8 Y5 AA5 AA2 AA1 W6 W7 Y3 Y4 V8 V9 Y1 Y2 V5 W5 V7 V6 W3 W4 U8 U9 W1 W2 U7 U6 U4 V4 U3 V3 T5 U5 U2
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
3 -6 2
v2.7
Axcelerator Family FPGAs
896-Pin FBGA AX2000 Function IO293PB6F27 IO294NB6F27 IO294PB6F27 IO296NB6F27 IO296PB6F27 IO298NB6F27 IO298PB6F27 IO299NB6F27 IO299PB6F27 Bank 7 IO300NB7F28 IO300PB7F28 IO302NB7F28 IO302PB7F28 IO303NB7F28 IO303PB7F28 IO304NB7F28 IO304PB7F28 IO306NB7F28 IO306PB7F28 IO307NB7F28 IO307PB7F28 IO308NB7F28 IO308PB7F28 IO309NB7F28 IO309PB7F28 IO310NB7F29 IO310PB7F29 IO311NB7F29 IO311PB7F29 IO312NB7F29 IO312PB7F29 IO313NB7F29 IO313PB7F29 R8 R9 R4 R5 P1 R1 R7 R6 N2 P2 N3 P3 P9 P8 P4 P5 P7 P6 L1 M1 M5 N5 M4 N4 Pin Number V2 T8 T9 T1 U1 T7 T6 R2 T2
896-Pin FBGA AX2000 Function IO315NB7F29 IO315PB7F29 IO316NB7F29 IO316PB7F29 IO317NB7F29 IO317PB7F29 IO318NB7F29 IO318PB7F29 IO320NB7F29 IO320PB7F29 IO321NB7F30 IO321PB7F30 IO322NB7F30 IO322PB7F30 IO323NB7F30 IO323PB7F30 IO324NB7F30 IO324PB7F30 IO326NB7F30 IO326PB7F30 IO327NB7F30 IO327PB7F30 IO328NB7F30 IO328PB7F30 IO329NB7F30 IO329PB7F30 IO330NB7F30 IO330PB7F30 IO331NB7F30 IO331PB7F30 IO332NB7F31 IO332PB7F31 IO333NB7F31 IO333PB7F31 Pin Number L2 M2 N7 N6 L3 M3 N8 N9 L6 M6 K4 L4 M8 M7 J1 K1 K5 L5 G1* K2* J4 J3 L8 L7 G2 H2 G3 H3 K8 K7 J6 K6 D1 D2
896-Pin FBGA AX2000 Function IO334NB7F31 IO334PB7F31 IO335NB7F31 IO335PB7F31 IO336NB7F31 IO336PB7F31 IO337NB7F31 IO337PB7F31 IO338NB7F31 IO338PB7F31 IO339NB7F31 IO339PB7F31 IO340NB7F31 IO340PB7F31 IO341NB7F31 IO341PB7F31 Dedicated I/O GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND A13 A18 A2 A23 A29 A8 AA10 AA21 AA28 AA3 AB2 AB22 AB29 AB9 AC1 AC30 AE25 Pin Number G4 H4 F2 F1 H5 J5 E2 E1 H7 J7 F4 F3 F5 G5 G6 H6
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
v2.7
3-63
Axcelerator Family FPGAs
896-Pin FBGA AX2000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AE6 AF26 AF5 AG27 AG4 AH10 AH15 AH16 AH21 AH28 AH3 AJ1 AJ2 AJ22 AJ29 AJ30 AJ9 AK13 AK18 AK2 AK23 AK29 AK8 B1 B2 B22 B29 B30 B9 C10 C15 C16 C21 C28
896-Pin FBGA AX2000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number C3 D27 D28 D4 E26 E5 H1 H30 J2 J22 J29 J9 K10 K21 K28 K3 L11 L20 M12 M13 M14 M15 M16 M17 M18 M19 N1 N12 N13 N14 N15 N16 N17 N18
896-Pin FBGA AX2000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number N19 N30 P12 P13 P14 P15 P16 P17 P18 P19 R12 R13 R14 R15 R16 R17 R18 R19 R28 R3 T12 T13 T14 T15 T16 T17 T18 T19 T28 T3 U12 U13 U14 U15
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
3 -6 4
v2.7
Axcelerator Family FPGAs
896-Pin FBGA AX2000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND/LP PRA PRB PRC PRD TCK TDI TDO TMS TRST Pin Number U16 U17 U18 U19 V1 V12 V13 V14 V15 V16 V17 V18 V19 V30 W12 W13 W14 W15 W16 W17 W18 W19 Y11 Y20 E4 G15 D16 AB16 AF16 G7 D5 J8 F6 C4
896-Pin FBGA AX2000 Function VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA Pin Number AD6 AH26 E28 E3 L12 L13 L14 L15 L16 L17 L18 L19 M11 M20 N11 N20 P11 P20 R11 R20 T11 T20 U11 U20 V11 V20 W11 W20 Y12 Y13 Y14 Y15 Y16 Y17
896-Pin FBGA AX2000 Function VCCA VCCA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 Pin Number Y18 Y19 AD24 AD7 AE15 AE16 AF12 AF13 AF15 AF18 AF19 AH27 AH4 C13 C27 C5 D13 D19 D3 E18 F15 F16 F26 G16 T25 T4 A3 B3 J10 J11 J12 K11 K12 K13
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
v2.7
3-65
Axcelerator Family FPGAs
896-Pin FBGA AX2000 Function VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 Pin Number K14 K15 A28 B28 J19 J20 J21 K16 K17 K18 K19 K20 C29 C30 K22 L21 L22 M21 M22 N21 P21 R21 AA22 AH29 AH30 T21 U21 V21 W21 W22 Y21 Y22 AA16 AA17
896-Pin FBGA AX2000 Function VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 Pin Number AA18 AA19 AA20 AB19 AB20 AB21 AJ28 AK28 AA11 AA12 AA13 AA14 AA15 AB10 AB11 AB12 AJ3 AK3 AA9 AH1 AH2 T10 U10 V10 W10 W9 Y10 Y9 C1 C2 K9 L10 L9 M10
896-Pin FBGA AX2000 Function VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number M9 N10 P10 R10 G14 H15 G17 J16 AH17 AC16 AH14 AD15 F14 J15 F17 H16 AF17 AD16 AF14 AB15 G24
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
3 -6 6
v2.7
Axcelerator Family FPGAs
1152-Pin FBGA
A1 Ball Pad Corner 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP
Figure 3-8 * 1152-Pin FBGA (Bottom View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v2.7
3-67
Axcelerator Family FPGAs
1152-Pin FBGA AX2000 Function Bank 0 IO00NB0F0 IO00PB0F0 IO01NB0F0 IO01PB0F0 IO02NB0F0 IO02PB0F0 IO03NB0F0 IO03PB0F0 IO04NB0F0 IO04PB0F0 IO05NB0F0 IO05PB0F0 IO06NB0F0 IO06PB0F0 IO07NB0F0 IO07PB0F0 IO08NB0F0 IO08PB0F0 IO09NB0F0 IO09PB0F0 IO10NB0F0 IO10PB0F0 IO11NB0F0 IO11PB0F0 IO12NB0F1 IO12PB0F1 IO13NB0F1 IO13PB0F1 IO14NB0F1 IO14PB0F1 IO15NB0F1 IO15PB0F1 IO16NB0F1 IO16PB0F1 IO17NB0F1 IO17PB0F1 IO18NB0F1 IO18PB0F1 D6 C6 H10 H9 F8 G8 A6 B6 C7 D7 K10 J10 F9 G9 F10 G10 E9 E8 J11 K11 C8 D8 K12 J12 G11 H11 G12 H12 A7 B7 H13 J13 C9 D9 F12 F11 E11 E10 Pin Number
1152-Pin FBGA AX2000 Function IO19NB0F1 IO19PB0F1 IO20NB0F1 IO20PB0F1 IO21NB0F1 IO21PB0F1 IO22NB0F2 IO22PB0F2 IO23NB0F2 IO23PB0F2 IO24NB0F2 IO24PB0F2 IO25NB0F2 IO25PB0F2 IO26NB0F2 IO26PB0F2 IO27NB0F2 IO27PB0F2 IO28NB0F2 IO28PB0F2 IO29NB0F2 IO29PB0F2 IO30NB0F2 IO30PB0F2 IO31NB0F2 IO31PB0F2 IO32NB0F2 IO32PB0F2 IO33NB0F2 IO33PB0F2 IO34NB0F3 IO34PB0F3 IO35NB0F3 IO35PB0F3 IO36NB0F3 IO36PB0F3 IO37NB0F3 IO37PB0F3 IO38NB0F3 Pin Number F13 G13 A10 A9 K14 K13 B11 B10 C12 C11 A12 A11 H14 J14 D13 D12 F14 G14 E14 E13 B13 B12 C14 C13 H15 J15 A14 B14 K15 L15 D15 D14 A15 B15 B16 A16 G16 G15 D16
1152-Pin FBGA AX2000 Function IO38PB0F3 IO39NB0F3 IO39PB0F3 IO40NB0F3 IO40PB0F3 IO41NB0F3/HCLKAN IO41PB0F3/HCLKAP IO42NB0F3/HCLKBN IO42PB0F3/HCLKBP Bank 1 IO43NB1F4/HCLKCN IO43PB1F4/HCLKCP IO44NB1F4/HCLKDN IO44PB1F4/HCLKDP IO45NB1F4 IO45PB1F4 IO46NB1F4 IO46PB1F4 IO47NB1F4 IO47PB1F4 IO48NB1F4 IO48PB1F4 IO49NB1F4 IO49PB1F4 IO50NB1F4 IO50PB1F4 IO51NB1F4 IO51PB1F4 IO52NB1F4 IO52PB1F4 IO53NB1F4 IO53PB1F4 IO54NB1F5 IO54PB1F5 IO55NB1F5 IO55PB1F5 IO56NB1F5 IO56PB1F5 IO57NB1F5 G19 G18 E19 F19 C18 D18 A18 B18 K19 L19 C19 D19 K20 L20 A19 B19 H20 J20 B20 A20 F20 E20 B21 A21 K21 J21 D21 C21 G22 Pin Number C16 K16 L16 D17 C17 E16 F16 G17 F17
3 -6 8
v2.7
Axcelerator Family FPGAs
1152-Pin FBGA AX2000 Function IO57PB1F5 IO58NB1F5 IO58PB1F5 IO59NB1F5 IO59PB1F5 IO60NB1F5 IO60PB1F5 IO61NB1F5 IO61PB1F5 IO62NB1F5 IO62PB1F5 IO63NB1F5 IO63PB1F5 IO64NB1F6 IO64PB1F6 IO65NB1F6 IO65PB1F6 IO66NB1F6 IO66PB1F6 IO67NB1F6 IO67PB1F6 IO68NB1F6 IO68PB1F6 IO69NB1F6 IO69PB1F6 IO70NB1F6 IO70PB1F6 IO71NB1F6 IO71PB1F6 IO72NB1F6 IO72PB1F6 IO73NB1F6 IO73PB1F6 IO74NB1F6 IO74PB1F6 IO75NB1F6 IO75PB1F6 IO76NB1F7 IO76PB1F7 Pin Number G21 E22 E21 D22 C22 B23 A23 H22 H21 C24 C23 F23 F22 B24 A24 J22 K22 B25 A25 K23 J23 F24 E24 C27 C26 H24 G24 H23 G23 B28 A28 E26 E25 F26 F25 K25 K24 D27 D26
1152-Pin FBGA AX2000 Function IO77NB1F7 IO77PB1F7 IO78NB1F7 IO78PB1F7 IO79NB1F7 IO79PB1F7 IO80NB1F7 IO80PB1F7 IO81NB1F7 IO81PB1F7 IO82NB1F7 IO82PB1F7 IO83NB1F7 IO83PB1F7 IO84NB1F7 IO84PB1F7 IO85NB1F7 IO85PB1F7 Bank 2 IO86NB2F8 IO86PB2F8 IO87NB2F8 IO87PB2F8 IO88NB2F8 IO88PB2F8 IO89NB2F8 IO89PB2F8 IO90NB2F8 IO90PB2F8 IO91NB2F8 IO91PB2F8 IO92NB2F8 IO92PB2F8 IO93NB2F8 IO93PB2F8 IO94NB2F8 IO94PB2F8 IO95NB2F8 IO95PB2F8 J28 J27 M25 L25 L26 K26 G31 F31 H29 G29 K28 K27 J30 H30 L28 L27 K29 J29 K31 J31 Pin Number B29 A29 D28 C28 H25 G25 F27 E27 J25 J24 D29 C29 H26 G26 F28 E28 H27 G27
1152-Pin FBGA AX2000 Function IO96NB2F9 IO96PB2F9 IO97NB2F9 IO97PB2F9 IO98NB2F9 IO98PB2F9 IO99NB2F9 IO99PB2F9 IO100NB2F9 IO100PB2F9 IO101NB2F9 IO101PB2F9 IO102NB2F9 IO102PB2F9 IO103NB2F9 IO103PB2F9 IO104NB2F9 IO104PB2F9 IO105NB2F9 IO105PB2F9 IO106NB2F9 IO106PB2F9 IO107NB2F10 IO107PB2F10 IO108NB2F10 IO108PB2F10 IO109NB2F10 IO109PB2F10 IO110NB2F10 IO110PB2F10 IO111NB2F10 IO111PB2F10 IO112NB2F10 IO112PB2F10 IO113NB2F10 IO113PB2F10 IO114NB2F10 IO114PB2F10 IO115NB2F10 Pin Number J32 H32 M27 M26 L30 K30 N25 N26 M29 L29 L33 L32 K34 K33 N28 M28 M34 L34 P27 N27 M32 M31 P25 P26 N33 M33 P29 N29 P30 N30 R24 R25 P31 N31 R28 P28 P32 N32 R30
v2.7
3-69
Axcelerator Family FPGAs
1152-Pin FBGA AX2000 Function IO115PB2F10 IO116NB2F10 IO116PB2F10 IO117NB2F10 IO117PB2F10 IO118NB2F11 IO118PB2F11 IO119NB2F11 IO119PB2F11 IO120NB2F11 IO120PB2F11 IO121NB2F11 IO121PB2F11 IO122NB2F11 IO122PB2F11 IO123NB2F11 IO123PB2F11 IO124NB2F11 IO124PB2F11 IO125NB2F11 IO125PB2F11 IO126NB2F11 IO126PB2F11 IO127NB2F11 IO127PB2F11 IO128NB2F11 IO128PB2F11 Bank 3 IO129NB3F12 IO129PB3F12 IO130NB3F12 IO130PB3F12 IO131NB3F12 IO131PB3F12 IO132NB3F12 IO132PB3F12 IO133NB3F12 IO133PB3F12 IO134NB3F12 V29 U29 V31 V32 V24 V25 W28 V28 W26 V26 W33 Pin Number R29 P34 P33 R27 R26 R34 R33 T24 T25 T33 T34 T27 T26 T30 T29 U28 T28 T31 T32 U24 U25 U33 U34 U26 U27 U31 U32
1152-Pin FBGA AX2000 Function IO134PB3F12 IO135NB3F12 IO135PB3F12 IO136NB3F12 IO136PB3F12 IO137NB3F12 IO137PB3F12 IO138NB3F12 IO138PB3F12 IO139NB3F13 IO139PB3F13 IO140NB3F13 IO140PB3F13 IO141NB3F13 IO141PB3F13 IO142NB3F13 IO142PB3F13 IO143NB3F13 IO143PB3F13 IO144NB3F13 IO144PB3F13 IO145NB3F13 IO145PB3F13 IO146NB3F13 IO146PB3F13 IO147NB3F13 IO147PB3F13 IO148NB3F13 IO148PB3F13 IO149NB3F13 IO149PB3F13 IO150NB3F14 IO150PB3F14 IO151NB3F14 IO151PB3F14 IO152NB3F14 IO152PB3F14 IO153NB3F14 IO153PB3F14 Pin Number V33 W25 W24 W31 W32 Y30 W30 Y29 W29 Y27 W27 AA33 Y33 Y25 Y24 AA31 Y31 AA28 Y28 AA34 Y34 AA26 Y26 AA29 AA30 AB30 AB29 AB32 AA32 AB27 AA27 AC31 AB31 AD33 AC33 AC28 AB28 AB25 AA25
1152-Pin FBGA AX2000 Function IO154NB3F14 IO154PB3F14 IO155NB3F14 IO155PB3F14 IO156NB3F14 IO156PB3F14 IO157NB3F14 IO157PB3F14 IO158NB3F14 IO158PB3F14 IO159NB3F14 IO159PB3F14 IO160NB3F14 IO160PB3F14 IO161NB3F15 IO161PB3F15 IO162NB3F15 IO162PB3F15 IO163NB3F15 IO163PB3F15 IO164NB3F15 IO164PB3F15 IO165NB3F15 IO165PB3F15 IO166NB3F15 IO166PB3F15 IO167NB3F15 IO167PB3F15 IO168NB3F15 IO168PB3F15 IO169NB3F15 IO169PB3F15 IO170NB3F15 IO170PB3F15 Bank 4 IO171NB4F16 IO171PB4F16 IO172NB4F16 IO172PB4F16 AP29 AN29 AH26 AH27 Pin Number AD32 AC32 AD29 AC29 AE30 AD30 AC26 AB26 AH33 AG33 AD27 AC27 AG32 AF32 AG31 AF31 AF29 AE29 AE28 AD28 AG30 AF30 AE26 AD26 AJ30 AH30 AG28 AF28 AF27 AE27 AH29 AG29 AD25 AC25
3 -7 0
v2.7
Axcelerator Family FPGAs
1152-Pin FBGA AX2000 Function IO173NB4F16 IO173PB4F16 IO174NB4F16 IO174PB4F16 IO175NB4F16 IO175PB4F16 IO176NB4F16 IO176PB4F16 IO177NB4F16 IO177PB4F16 IO178NB4F16 IO178PB4F16 IO179NB4F16 IO179PB4F16 IO180NB4F16 IO180PB4F16 IO181NB4F17 IO181PB4F17 IO182NB4F17 IO182PB4F17 IO183NB4F17 IO183PB4F17 IO184NB4F17 IO184PB4F17 IO185NB4F17 IO185PB4F17 IO186NB4F17 IO186PB4F17 IO187NB4F17 IO187PB4F17 IO188NB4F17 IO188PB4F17 IO189NB4F17 IO189PB4F17 IO190NB4F17 IO190PB4F17 IO191NB4F17 IO191PB4F17 IO192NB4F17 Pin Number AJ27 AJ28 AL27 AL28 AM28 AM29 AG25 AG26 AK26 AK27 AF25 AE25 AP28 AN28 AJ25 AJ26 AM26 AM27 AF24 AE24 AH24 AH25 AG23 AG24 AL25 AL26 AP25 AP26 AK24 AK25 AF23 AE23 AN24 AM24 AH22 AH23 AJ23 AJ24 AG21
1152-Pin FBGA AX2000 Function IO192PB4F17 IO193NB4F18 IO193PB4F18 IO194NB4F18 IO194PB4F18 IO195NB4F18 IO195PB4F18 IO196NB4F18 IO196PB4F18 IO197NB4F18 IO197PB4F18 IO198NB4F18 IO198PB4F18 IO199NB4F18 IO199PB4F18 IO200NB4F18 IO200PB4F18 IO201NB4F18 IO201PB4F18 IO202NB4F18 IO202PB4F18 IO203NB4F19 IO203PB4F19 IO204NB4F19 IO204PB4F19 IO205NB4F19 IO205PB4F19 IO206NB4F19 IO206PB4F19 IO207NB4F19 IO207PB4F19 IO208NB4F19 IO208PB4F19 IO209NB4F19 IO209PB4F19 IO210NB4F19 IO210PB4F19 IO211NB4F19 IO211PB4F19 Pin Number AG22 AP23 AP24 AN22 AN23 AM23 AL23 AF21 AF22 AL22 AM22 AE21 AE22 AJ21 AJ22 AK21 AK22 AM21 AL21 AE20 AD20 AN21 AP21 AP20 AN20 AN19 AP19 AG20 AF20 AL19 AL20 AG19 AF19 AN18 AP18 AE19 AD19 AL18 AM18
1152-Pin FBGA AX2000 Function IO212NB4F19/CLKEN IO212PB4F19/CLKEP IO213NB4F19/CLKFN IO213PB4F19/CLKFP Bank 5 IO214NB5F20/CLKGN IO214PB5F20/CLKGP IO215NB5F20/CLKHN IO215PB5F20/CLKHP IO216NB5F20 IO216PB5F20 IO217NB5F20 IO217PB5F20 IO218NB5F20 IO218PB5F20 IO219NB5F20 IO219PB5F20 IO220NB5F20 IO220PB5F20 IO221NB5F20 IO221PB5F20 IO222NB5F20 IO222PB5F20 IO223NB5F21 IO223PB5F21 IO224NB5F21 IO224PB5F21 IO225NB5F21 IO225PB5F21 IO226NB5F21 IO226PB5F21 IO227NB5F21 IO227PB5F21 IO228NB5F21 IO228PB5F21 IO229NB5F21 IO229PB5F21 IO230NB5F21 IO230PB5F21 AJ16 AJ17 AJ15 AK15 AD16 AE17 AM17 AL17 AG16 AF16 AM16 AL16 AP16 AN16 AN15 AP15 AD15 AE16 AL14 AL15 AN14 AP14 AK13 AK14 AE15 AF15 AG14 AG15 AJ13 AJ14 AM13 AM14 AE14 AF14 Pin Number AJ20 AK20 AJ18 AJ19
v2.7
3-71
Axcelerator Family FPGAs
1152-Pin FBGA AX2000 Function IO231NB5F21 IO231PB5F21 IO232NB5F21 IO232PB5F21 IO233NB5F21 IO233PB5F21 IO234NB5F21 IO234PB5F21 IO235NB5F22 IO235PB5F22 IO236NB5F22 IO236PB5F22 IO237NB5F22 IO237PB5F22 IO238NB5F22 IO238PB5F22 IO239NB5F22 IO239PB5F22 IO240NB5F22 IO240PB5F22 IO241NB5F22 IO241PB5F22 IO242NB5F22 IO242PB5F22 IO243NB5F22 IO243PB5F22 IO244NB5F22 IO244PB5F22 IO245NB5F23 IO245PB5F23 IO246NB5F23 IO246PB5F23 IO247NB5F23 IO247PB5F23 IO248NB5F23 IO248PB5F23 IO249NB5F23 IO249PB5F23 IO250NB5F23 Pin Number AN12 AP12 AG13 AH13 AL12 AL13 AE13 AF13 AN11 AP11 AM11 AM12 AJ11 AJ12 AH11 AH12 AK10 AK11 AE12 AF12 AN10 AP10 AG11 AG12 AL9 AL10 AM8 AM9 AH10 AJ10 AF10 AF11 AJ9 AK9 AN7 AP7 AL7 AL8 AE10
1152-Pin FBGA AX2000 Function IO250PB5F23 IO251NB5F23 IO251PB5F23 IO252NB5F23 IO252PB5F23 IO253NB5F23 IO253PB5F23 IO254NB5F23 IO254PB5F23 IO255NB5F23 IO255PB5F23 IO256NB5F23 IO256PB5F23 Bank 6 IO257NB6F24 IO257PB6F24 IO258NB6F24 IO258PB6F24 IO259NB6F24 IO259PB6F24 IO260NB6F24 IO260PB6F24 IO261NB6F24 IO261PB6F24 IO262NB6F24 IO262PB6F24 IO263NB6F24 IO263PB6F24 IO264NB6F24 IO264PB6F24 IO265NB6F24 IO265PB6F24 IO266NB6F24 IO266PB6F24 IO267NB6F25 IO267PB6F25 IO268NB6F25 IO268PB6F25 IO269NB6F25 AG6 AH6 AD9 AE9 AF7 AG7 AH3 AH4 AH5 AJ5 AE6 AF6 AF5 AG5 AD8 AE8 AF3 AG3 AC10 AD10 AD7 AE7 AD5 AE5 AE4 Pin Number AE11 AK8 AJ8 AH8 AH9 AN6 AP6 AG9 AG10 AJ7 AK7 AL6 AM6
1152-Pin FBGA AX2000 Function IO269PB6F25 IO270NB6F25 IO270PB6F25 IO271NB6F25 IO271PB6F25 IO272NB6F25 IO272PB6F25 IO273NB6F25 IO273PB6F25 IO274NB6F25 IO274PB6F25 IO275NB6F25 IO275PB6F25 IO276NB6F25 IO276PB6F25 IO277NB6F25 IO277PB6F25 IO278NB6F26 IO278PB6F26 IO279NB6F26 IO279PB6F26 IO280NB6F26 IO280PB6F26 IO281NB6F26 IO281PB6F26 IO282NB6F26 IO282PB6F26 IO283NB6F26 IO283PB6F26 IO284NB6F26 IO284PB6F26 IO285NB6F26 IO285PB6F26 IO286NB6F26 IO286PB6F26 IO287NB6F26 IO287PB6F26 IO288NB6F26 IO288PB6F26 Pin Number AF4 AB9 AC9 AC6 AD6 AB8 AC8 AE1 AE2 AA10 AB10 AB7 AC7 AD1 AD2 AC4 AC3 AA8 AA9 AB5 AB6 Y10 Y11 AB3 AB4 Y7 AA7 AC2 AC1 Y9 Y8 AA5 AA6 W10 W11 AA3 AA4 W9 W8
3 -7 2
v2.7
Axcelerator Family FPGAs
1152-Pin FBGA AX2000 Function IO289NB6F27 IO289PB6F27 IO290NB6F27 IO290PB6F27 IO291NB6F27 IO291PB6F27 IO292NB6F27 IO292PB6F27 IO293NB6F27 IO293PB6F27 IO294NB6F27 IO294PB6F27 IO295NB6F27 IO295PB6F27 IO296NB6F27 IO296PB6F27 IO297NB6F27 IO297PB6F27 IO298NB6F27 IO298PB6F27 IO299NB6F27 IO299PB6F27 Bank 7 IO300NB7F28 IO300PB7F28 IO301NB7F28 IO301PB7F28 IO302NB7F28 IO302PB7F28 IO303NB7F28 IO303PB7F28 IO304NB7F28 IO304PB7F28 IO305NB7F28 IO305PB7F28 IO306NB7F28 IO306PB7F28 IO307NB7F28 IO307PB7F28 U10 U11 U2 U1 U6 U7 T3 U3 U9 U8 R2 R1 R4 T4 R5 T5 Pin Number AA1 AA2 W6 Y6 W5 Y5 V7 W7 W4 Y4 V10 V11 Y1 Y2 W1 W2 V1 V2 V9 V8 U4 V4
1152-Pin FBGA AX2000 Function IO308NB7F28 IO308PB7F28 IO309NB7F28 IO309PB7F28 IO310NB7F29 IO310PB7F29 IO311NB7F29 IO311PB7F29 IO312NB7F29 IO312PB7F29 IO313NB7F29 IO313PB7F29 IO314NB7F29 IO314PB7F29 IO315NB7F29 IO315PB7F29 IO316NB7F29 IO316PB7F29 IO317NB7F29 IO317PB7F29 IO318NB7F29 IO318PB7F29 IO319NB7F29 IO319PB7F29 IO320NB7F29 IO320PB7F29 IO321NB7F30 IO321PB7F30 IO322NB7F30 IO322PB7F30 IO323NB7F30 IO323PB7F30 IO324NB7F30 IO324PB7F30 IO325NB7F30 IO325PB7F30 IO326NB7F30 IO326PB7F30 IO327NB7F30 Pin Number T11 T10 T6 T7 T9 T8 N3 P3 P7 R7 P6 R6 M2 N2 N4 P4 R9 R8 N5 P5 R10 R11 L2 L1 N8 P8 M6 N6 P10 P9 L3 M3 M7 N7 K2 K1 G2 H2 L6
1152-Pin FBGA AX2000 Function IO327PB7F30 IO328NB7F30 IO328PB7F30 IO329NB7F30 IO329PB7F30 IO330NB7F30 IO330PB7F30 IO331NB7F30 IO331PB7F30 IO332NB7F31 IO332PB7F31 IO333NB7F31 IO333PB7F31 IO334NB7F31 IO334PB7F31 IO335NB7F31 IO335PB7F31 IO336NB7F31 IO336PB7F31 IO337NB7F31 IO337PB7F31 IO338NB7F31 IO338PB7F31 IO339NB7F31 IO339PB7F31 IO340NB7F31 IO340PB7F31 IO341NB7F31 IO341PB7F31 Dedicated I/O GND GND GND GND GND GND GND GND GND A13 A2 A22 A27 A3 A31 A32 A33 A4 Pin Number L5 N10 N9 J4 K4 J5 K5 M10 M9 L8 M8 F2 F1 J6 K6 H4 H3 K7 L7 G4 G3 K9 L9 H6 H5 H7 J7 J8 K8
v2.7
3-73
Axcelerator Family FPGAs
1152-Pin FBGA AX2000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number A8 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AB1 AB13 AB22 AB34 AC12 AC23 AC30 AC5 AD11 AD24 AD31 AD4 AE3 AE32 AF2 AF33 AG1 AG27 AG34 AG8 AH28 AH7 AJ29 AJ6 AK12 AK17 AK18 AK23 AK30 AK5
1152-Pin FBGA AX2000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AL1 AL11 AL2 AL24 AL3 AL31 AL32 AL33 AL34 AL4 AM1 AM10 AM15 AM2 AM20 AM25 AM3 AM31 AM32 AM33 AM34 AM4 AN1 AN2 AN26 AN3 AN31 AN32 AN33 AN34 AN4 AN9 AP13 AP2 AP22 AP27 AP3 AP31 AP32
1152-Pin FBGA AX2000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AP33 AP4 AP8 B1 B2 B26 B3 B31 B32 B33 B34 B4 B9 C1 C10 C15 C2 C20 C25 C3 C31 C32 C33 C34 C4 D1 D11 D2 D24 D3 D31 D32 D33 D34 D4 E12 E17 E18 E23
3 -7 4
v2.7
Axcelerator Family FPGAs
1152-Pin FBGA AX2000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number E30 E5 F29 F30 F6 G28 G7 H1 H34 J2 J33 K3 K32 L11 L24 L31 L4 M12 M23 M30 M5 N1 N13 N22 N34 P14 P15 P16 P17 P18 P19 P20 P21 R14 R15 R16 R17 R18 R19
1152-Pin FBGA AX2000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number R20 R21 R3 R32 T14 T15 T16 T17 T18 T19 T20 T21 U14 U15 U16 U17 U18 U19 U20 U21 U30 U5 V14 V15 V16 V17 V18 V19 V20 V21 V30 V5 W14 W15 W16 W17 W18 W19 W20
1152-Pin FBGA AX2000 Function GND GND GND GND GND GND GND GND GND GND GND GND/LP NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin Number W21 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y3 Y32 G6 A17 A26 AB2 AB33 AC34 AD3 AD34 AE31 AE33 AE34 AF1 AF34 AG2 AG4 AH1 AH2 AH31 AH32 AH34 AJ1 AJ2 AJ3 AJ31 AJ32 AJ33 AJ34 AJ4
v2.7
3-75
Axcelerator Family FPGAs
1152-Pin FBGA AX2000 Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC Pin Number AL29 AM19 AM7 AN13 AN17 AN25 AN27 AN8 AP17 AP9 B17 B22 B27 B8 D10 D20 D23 D25 F3 F32 F33 F34 F4 G1 G32 G33 G34 H31 H33 J1 J3 J34 M1 M4 P1 P2 R31 T1 T2
1152-Pin FBGA AX2000 Function NC NC NC NC PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA Pin Number V3 V34 W3 W34 J17 F18 AD18 AH18 J9 F7 L10 H8 E6 AA13 AA22 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AF8 AK28 G30 G5 N14 N15 N16 N17 N18 N19 N20 N21 P13 P22 R13 R22
1152-Pin FBGA AX2000 Function VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 Pin Number T13 T22 U13 U22 V13 V22 W13 W22 Y13 Y22 AF26 AF9 AG17 AG18 AH14 AH15 AH17 AH20 AH21 AK29 AK6 E15 E29 E7 F15 F21 F5 G20 H17 H18 H28 J18 V27 V6 A5 B5 C5 D5 L12
3 -7 6
v2.7
Axcelerator Family FPGAs
1152-Pin FBGA AX2000 Function VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 Pin Number L13 L14 M13 M14 M15 M16 M17 A30 B30 C30 D30 L21 L22 L23 M18 M19 M20 M21 M22 E31 E32 E33 E34 M24 N23 N24 P23 P24 R23 T23 U23 AA23 AA24 AB23 AB24 AC24 AK31 AK32 AK33
1152-Pin FBGA AX2000 Function VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 Pin Number AK34 V23 W23 Y23 AC18 AC19 AC20 AC21 AC22 AD21 AD22 AD23 AL30 AM30 AN30 AP30 AC13 AC14 AC15 AC16 AC17 AD12 AD13 AD14 AL5 AM5 AN5 AP5 AA11 AA12 AB11 AB12 AC11 AK1 AK2 AK3 AK4 V12 W12
1152-Pin FBGA AX2000 Function VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number Y12 E1 E2 E3 E4 M11 N11 N12 P11 P12 R12 T12 U12 J16 K17 J19 L18 AK19 AE18 AK16 AF17 H16 L17 H19 K18 AH19 AF18 AH16 AD17 J26
v2.7
3-77
Axcelerator Family FPGAs
208-Pin PQFP
1
208
208-Pin PQFP
Figure 3-9 * 208-Pin PQFP
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
3 -7 8
v2.7
Axcelerator Family FPGAs
208-Pin PQFP AX250 Function Bank 0 IO02NB0F0 IO03NB0F0 IO03PB0F0 IO12NB0F0/HCLKAN IO12PB0F0/HCLKAP IO13NB0F0/HCLKBN IO13PB0F0/HCLKBP Bank 1 IO14NB1F1/HCLKCN IO14PB1F1/HCLKCP IO15NB1F1/HCLKDN IO15PB1F1/HCLKDP IO16NB1F1 IO16PB1F1 IO24NB1F1 IO24PB1F1 IO26NB1F1 IO26PB1F1 IO27NB1F1 IO27PB1F1 Bank 2 IO29NB2F2 IO29PB2F2 IO30NB2F2 IO30PB2F2 IO31PB2F2 IO32NB2F2 IO32PB2F2 IO34NB2F2 IO34PB2F2 IO39NB2F2 IO39PB2F2 IO40PB2F2 IO41NB2F2 IO41PB2F2 IO43NB2F2 IO43PB2F2 151 153 152 154 148 146 147 144 145 139 140 141 137 138 132 134 180 181 174 175 170 171 165 166 161 162 159 160 197 198 199 191 192 185 186 Pin Number
208-Pin PQFP AX250 Function IO44NB2F2 IO44PB2F2 Bank 3 IO45NB3F3 IO45PB3F3 IO46NB3F3 IO46PB3F3 IO48NB3F3 IO48PB3F3 IO50NB3F3 IO50PB3F3 IO55NB3F3 IO55PB3F3 IO57NB3F3 IO57PB3F3 IO59NB3F3 IO59PB3F3 IO60NB3F3 IO60PB3F3 IO61NB3F3 IO61PB3F3 Bank 4 IO62NB4F4 IO62PB4F4 IO63NB4F4 IO63PB4F4 IO64NB4F4 IO64PB4F4 IO72NB4F4 IO72PB4F4 IO74NB4F4/CLKEN IO74PB4F4/CLKEP IO75NB4F4/CLKFN IO75PB4F4/CLKFP Bank 5 IO76NB5F5/CLKGN IO76PB5F5/CLKGP IO77NB5F5/CLKHN 76 77 70 100 103 101 102 96 97 91 92 87 88 81 82 127 129 126 128 122 123 120 121 116 117 114 115 110 111 108 109 106 107 Pin Number 131 133
208-Pin PQFP AX250 Function IO77PB5F5/CLKHP IO78NB5F5 IO78PB5F5 IO86NB5F5 IO87NB5F5 IO87PB5F5 IO88NB5F5 IO88PB5F5 IO89NB5F5 IO89PB5F5 Bank 6 IO91NB6F6 IO91PB6F6 IO92NB6F6 IO92PB6F6 IO93NB6F6 IO93PB6F6 IO94PB6F6 IO96NB6F6 IO96PB6F6 IO101NB6F6 IO101PB6F6 IO102PB6F6 IO103NB6F6 IO103PB6F6 IO105NB6F6 IO105PB6F6 IO106NB6F6 IO106PB6F6 Bank 7 IO107NB7F7 IO107PB7F7 IO108NB7F7 IO108PB7F7 IO110NB7F7 IO110PB7F7 IO112NB7F7 IO112PB7F7 23 25 22 24 18 19 16 17 47 49 48 50 42 43 44 40 41 35 36 37 33 34 28 30 27 29 Pin Number 71 66 67 62 60 61 56 57 54 55
v2.7
3-79
Axcelerator Family FPGAs
208-Pin PQFP AX250 Function IO117NB7F7 IO117PB7F7 IO119NB7F7 IO119PB7F7 IO121PB7F7 IO122NB7F7 IO122PB7F7 IO123NB7F7 IO123PB7F7 Dedicated I/O VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 1 26 53 63 78 95 105 130 157 167 182 202 104 9 15 21 32 39 46 51 59 65 69 90 94 99 113 119 Pin Number 12 13 10 11 7 5 6 3 4
208-Pin PQFP AX250 Function GND GND GND GND GND GND GND GND GND GND GND GND/LP PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF Pin Number 125 136 143 150 155 164 169 173 194 196 201 208 184 183 80 79 205 204 203 206 207 2 52 156 14 38 64 93 118 142 168 195 189 187 178 176 85 83
208-Pin PQFP AX250 Function VCCPLG VCCPLH VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number 74 72 193 200 163 172 135 149 112 124 89 98 58 68 31 45 8 20 190 188 179 177 86 84 75 73 158
3 -8 0
v2.7
Axcelerator Family FPGAs
208-Pin PQFP AX500 Function Bank 0 IO03NB0F0 IO03PB0F0 IO04NB0F0 IO19NB0F1/HCLKAN IO19PB0F1/HCLKAP IO20NB0F1/HCLKBN IO20PB0F1/HCLKBP Bank 1 IO21NB1F2/HCLKCN IO21PB1F2/HCLKCP IO22NB1F2/HCLKDN IO22PB1F2/HCLKDP IO23NB1F2 IO23PB1F2 IO37NB1F3 IO37PB1F3 IO39NB1F3 IO39PB1F3 IO41NB1F3 IO41PB1F3 Bank 2 IO43NB2F4 IO43PB2F4 IO44NB2F4 IO44PB2F4 IO45PB2F4 IO46NB2F4 IO46PB2F4 IO48NB2F4 IO48PB2F4 IO57NB2F5 IO57PB2F5 IO58PB2F5 IO59NB2F5 IO59PB2F5 IO61NB2F5 IO61PB2F5 151 153 152 154 148 146 147 144 145 139 140 141 137 138 132 134 180 181 174 175 170 171 165 166 161 162 159 160 198 199 197 191 192 185 186 Pin Number
208-Pin PQFP AX500 Function IO62NB2F5 IO62PB2F5 Bank 3 IO63NB3F6 IO63PB3F6 IO64NB3F6 IO64PB3F6 IO66NB3F6 IO66PB3F6 IO68NB3F6 IO68PB3F6 IO77NB3F7 IO77PB3F7 IO79NB3F7 IO79PB3F7 IO81NB3F7 IO81PB3F7 IO82NB3F7 IO82PB3F7 IO83NB3F7 IO83PB3F7 Bank 4 IO84PB4F8 IO85NB4F8 IO86NB4F8 IO86PB4F8 IO87NB4F8 IO87PB4F8 IO101NB4F9 IO101PB4F9 IO103NB4F9/CLKEN IO103PB4F9/CLKEP IO104NB4F9/CLKFN IO104PB4F9/CLKFP Bank 5 IO105NB5F10/CLKGN IO105PB5F10/CLKGP IO106NB5F10/CLKHN 76 77 70 103 100 101 102 96 97 91 92 87 88 81 82 127 129 126 128 122 123 120 121 116 117 114 115 110 111 108 109 106 107 Pin Number 131 133
208-Pin PQFP AX500 Function IO106PB5F10/CLKHP IO107NB5F10 IO107PB5F10 IO119NB5F11 IO121NB5F11 IO121PB5F11 IO123NB5F11 IO123PB5F11 IO125NB5F11 IO125PB5F11 Bank 6 IO127NB6F12 IO127PB6F12 IO128NB6F12 IO128PB6F12 IO129NB6F12 IO129PB6F12 IO130PB6F12 IO132NB6F12 IO132PB6F12 IO141NB6F13 IO141PB6F13 IO142PB6F13 IO143NB6F13 IO143PB6F13 IO145NB6F13 IO145PB6F13 IO146NB6F13 IO146PB6F13 Bank 7 IO147NB7F14 IO147PB7F14 IO148NB7F14 IO148PB7F14 IO150NB7F14 IO150PB7F14 IO152NB7F14 IO152PB7F14 23 25 22 24 18 19 16 17 47 49 48 50 42 43 44 40 41 35 36 37 33 34 28 30 27 29 Pin Number 71 66 67 62 60 61 56 57 54 55
v2.7
3-81
Axcelerator Family FPGAs
208-Pin PQFP AX500 Function IO161NB7F15 IO161PB7F15 IO163NB7F15 IO163PB7F15 IO165PB7F15 IO166NB7F15 IO166PB7F15 IO167NB7F15 IO167PB7F15 Dedicated I/O VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 1 26 53 63 78 95 105 130 157 167 182 202 104 9 15 21 32 39 46 51 59 65 69 90 94 99 113 119 Pin Number 12 13 10 11 7 5 6 3 4
208-Pin PQFP AX500 Function GND GND GND GND GND GND GND GND GND GND GND GND/LP PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF Pin Number 125 143 136 150 155 164 169 173 194 196 201 208 184 183 80 79 205 204 203 206 207 2 14 38 52 64 93 118 142 156 168 195 189 187 178 176 85 83
208-Pin PQFP AX500 Function VCCPLG VCCPLH VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number 74 72 200 193 172 163 149 135 124 112 98 89 68 58 45 31 20 8 190 188 179 177 86 84 75 73 158
3 -8 2
v2.7
Axcelerator Family FPGAs
208-Pin CQFP
1
208
208-Pin PQFP
Figure 3-10 * 208-Pin CQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
v2.7
3-83
Axcelerator Family FPGAs
208-Pin CQFP AX250 Function Bank 0 IO02NB0F0 IO03NB0F0 IO03PB0F0 IO12NB0F0/HCLKAN IO12PB0F0/HCLKAP IO13NB0F0/HCLKBN IO13PB0F0/HCLKBP Bank 1 IO14NB1F1/HCLKCN IO14PB1F1/HCLKCP IO15NB1F1/HCLKDN IO15PB1F1/HCLKDP IO16NB1F1 IO16PB1F1 IO24NB1F1 IO24PB1F1 IO26NB1F1 IO26PB1F1 IO27NB1F1 IO27PB1F1 Bank 2 IO29NB2F2 IO29PB2F2 IO30NB2F2 IO30PB2F2 IO31PB2F2 IO32NB2F2 IO32PB2F2 IO34NB2F2 IO34PB2F2 IO39NB2F2 IO39PB2F2 IO40PB2F2 IO41NB2F2 IO41PB2F2 IO43NB2F2 151 153 152 154 148 146 147 144 145 139 140 141 137 138 132 180 181 174 175 170 171 165 166 161 162 159 160 197 198 199 191 192 185 186 Pin #
208-Pin CQFP AX250 Function IO43PB2F2 IO44NB2F2 IO44PB2F2 Bank 3 IO45NB3F3 IO45PB3F3 IO46NB3F3 IO46PB3F3 IO48NB3F3 IO48PB3F3 IO50NB3F3 IO50PB3F3 IO55NB3F3 IO55PB3F3 IO57NB3F3 IO57PB3F3 IO59NB3F3 IO59PB3F3 IO60NB3F3 IO60PB3F3 IO61NB3F3 IO61PB3F3 Bank 4 IO62NB4F4 IO62PB4F4 IO63NB4F4 IO63PB4F4 IO64NB4F4 IO64PB4F4 IO72NB4F4 IO72PB4F4 IO74NB4F4/CLKEN IO74PB4F4/CLKEP IO75NB4F4/CLKFN IO75PB4F4/CLKFP Bank 5 IO76NB5F5/CLKGN 76 100 103 101 102 96 97 91 92 87 88 81 82 127 129 126 128 122 123 120 121 116 117 114 115 110 111 108 109 106 107 Pin # 134 131 133
208-Pin CQFP AX250 Function IO76PB5F5/CLKGP IO77NB5F5/CLKHN IO77PB5F5/CLKHP IO78NB5F5 IO78PB5F5 IO86NB5F5 IO87NB5F5 IO87PB5F5 IO88NB5F5 IO88PB5F5 IO89NB5F5 IO89PB5F5 Bank 6 IO91NB6F6 IO91PB6F6 IO92NB6F6 IO92PB6F6 IO93NB6F6 IO93PB6F6 IO94PB6F6 IO96NB6F6 IO96PB6F6 IO101NB6F6 IO101PB6F6 IO102PB6F6 IO103NB6F6 IO103PB6F6 IO105NB6F6 IO105PB6F6 IO106NB6F6 IO106PB6F6 Bank 7 IO107NB7F7 IO107PB7F7 IO108NB7F7 IO108PB7F7 IO110NB7F7 23 25 22 24 18 47 49 48 50 42 43 44 40 41 35 36 37 33 34 28 30 27 29 Pin # 77 70 71 66 67 62 60 61 56 57 54 55
3 -8 4
v2.7
Axcelerator Family FPGAs
208-Pin CQFP AX250 Function IO110PB7F7 IO112NB7F7 IO112PB7F7 IO117NB7F7 IO117PB7F7 IO119NB7F7 IO119PB7F7 IO121PB7F7 IO122NB7F7 IO122PB7F7 IO123NB7F7 IO123PB7F7 Dedicated I/O GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 9 15 21 32 39 46 51 59 65 69 90 94 99 104 113 119 125 136 143 150 155 164 169 173 Pin # 19 16 17 12 13 10 11 7 5 6 3 4
208-Pin CQFP AX250 Function GND GND GND GND/LP PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 Pin # 194 196 201 208 184 183 80 79 205 204 203 206 207 2 14 38 52 64 93 118 142 156 168 195 1 26 53 63 78 95 105 130 157 167 182 202 193
208-Pin CQFP AX250 Function VCCIB0 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin # 200 163 172 135 149 112 124 89 98 58 68 31 45 8 20 189 187 178 176 85 83 74 72 190 188 179 177 86 84 75 73 158
v2.7
3-85
Axcelerator Family FPGAs
208 CQFP AX500 Function Bank 0 IO03NB0F0 IO03PB0F0 IO04NB0F0 IO19NB0F1/HCLKAN IO19PB0F1/HCLKAP IO20NB0F1/HCLKBN IO20PB0F1/HCLKBP Bank 1 IO21NB1F2/HCLKCN IO21PB1F2/HCLKCP IO22NB1F2/HCLKDN IO22PB1F2/HCLKDP IO23NB1F2 IO23PB1F2 IO37NB1F3 IO37PB1F3 IO39NB1F3 IO39PB1F3 IO41NB1F3 IO41PB1F3 Bank 2 IO43NB2F4 IO43PB2F4 IO44NB2F4 IO44PB2F4 IO45PB2F4 IO46NB2F4 IO46PB2F4 IO48NB2F4 IO48PB2F4 IO57NB2F5 IO57PB2F5 IO58PB2F5 IO59NB2F5 IO59PB2F5 IO61NB2F5 151 153 152 154 148 146 147 144 145 139 140 141 137 138 132 180 181 174 175 170 171 165 166 161 162 159 160 198 199 197 191 192 185 186 Pin #
208 CQFP AX500 Function IO61PB2F5 IO62NB2F5 IO62PB2F5 Bank 3 IO63NB3F6 IO63PB3F6 IO64NB3F6 IO64PB3F6 IO66NB3F6 IO66PB3F6 IO68NB3F6 IO68PB3F6 IO77NB3F7 IO77PB3F7 IO79NB3F7 IO79PB3F7 IO81NB3F7 IO81PB3F7 IO82NB3F7 IO82PB3F7 IO83NB3F7 IO83PB3F7 Bank 4 IO84PB4F8 IO85NB4F8 IO86NB4F8 IO86PB4F8 IO87NB4F8 IO87PB4F8 IO101NB4F9 IO101PB4F9 IO103NB4F9/CLKEN IO103PB4F9/CLKEP IO104NB4F9/CLKFN IO104PB4F9/CLKFP Bank 5 IO105NB5F10/CLKGN 76 103 100 101 102 96 97 91 92 87 88 81 82 127 129 126 128 122 123 120 121 116 117 114 115 110 111 108 109 106 107 Pin # 134 131 133
208 CQFP AX500 Function IO105PB5F10/CLKGP IO106NB5F10/CLKHN IO106PB5F10/CLKHP IO107NB5F10 IO107PB5F10 IO119NB5F11 IO121NB5F11 IO121PB5F11 IO123NB5F11 IO123PB5F11 IO125NB5F11 IO125PB5F11 Bank 6 IO127NB6F12 IO127PB6F12 IO128NB6F12 IO128PB6F12 IO129NB6F12 IO129PB6F12 IO130PB6F12 IO132NB6F12 IO132PB6F12 IO141NB6F13 IO141PB6F13 IO142PB6F13 IO143NB6F13 IO143PB6F13 IO145NB6F13 IO145PB6F13 IO146NB6F13 IO146PB6F13 Bank 7 IO147NB7F14 IO147PB7F14 IO148NB7F14 IO148PB7F14 IO150NB7F14 23 25 22 24 18 47 49 48 50 42 43 44 40 41 35 36 37 33 34 28 30 27 29 Pin # 77 70 71 66 67 62 60 61 56 57 54 55
3 -8 6
v2.7
Axcelerator Family FPGAs
208 CQFP AX500 Function IO150PB7F14 IO152NB7F14 IO152PB7F14 IO161NB7F15 IO161PB7F15 IO163NB7F15 IO163PB7F15 IO165PB7F15 IO166NB7F15 IO166PB7F15 IO167NB7F15 IO167PB7F15 Dedicated I/O VCCDA GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 1 9 15 21 32 39 46 51 59 65 69 90 94 99 104 113 119 125 136 143 150 155 164 169 Pin # 19 16 17 12 13 10 11 7 5 6 3 4
208 CQFP AX500 Function GND GND GND GND GND/LP PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 Pin # 173 194 196 201 208 184 183 80 79 205 204 203 206 207 2 14 38 52 64 93 118 142 156 168 195 26 53 63 78 95 105 130 157 167 182 202 193
208 CQFP AX500 Function VCCIB0 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin # 200 163 172 135 149 112 124 89 98 58 68 31 45 8 20 189 187 178 176 85 83 74 72 190 188 179 177 86 84 75 73 158
v2.7
3-87
Axcelerator Family FPGAs
352-Pin CQFP
352 351 350 349 339 338 337 336 335 334 333 332 331 268 267 266 265
1 2 3 4
Pin 1
264 263 262 261
Ceramic Tie Bar
41 42 43 44 45 46 47 48 49
352-Pin CQFP
223 222 221 220 219 218 217 216 215
85 86 87 88
180 179 178 177
127 128 129 130 131 132 133 134 135
Figure 3-11 * 352-Pin CQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
3 -8 8
v2.7
173 174 175 176
89 90 91 92
Axcelerator Family FPGAs
352-Pin CQFP AX250 Function Bank 0 IO00NB0F0 IO00PB0F0 IO01NB0F0 IO02NB0F0 IO02PB0F0 IO04NB0F0 IO04PB0F0 IO06NB0F0 IO06PB0F0 IO08NB0F0 IO08PB0F0 IO10NB0F0 IO10PB0F0 IO12NB0F0/HCLKAN IO12PB0F0/HCLKAP IO13NB0F0/HCLKBN IO13PB0F0/HCLKBP Bank 1 IO14NB1F1/HCLKCN IO14PB1F1/HCLKCP IO15NB1F1/HCLKDN IO15PB1F1/HCLKDP IO16NB1F1 IO16PB1F1 IO17NB1F1 IO17PB1F1 IO18NB1F1 IO18PB1F1 IO20NB1F1 IO20PB1F1 IO22NB1F1 IO22PB1F1 IO23NB1F1 IO23PB1F1 IO24NB1F1 IO24PB1F1 305 306 299 300 289 290 295 296 287 288 283 284 277 278 281 282 275 276 341 342 343 337 338 335 336 331 332 325 326 323 324 319 320 313 314 Pin #
352-Pin CQFP AX250 Function IO25NB1F1 IO25PB1F1 IO27NB1F1 IO27PB1F1 Bank 2 IO29NB2F2 IO29PB2F2 IO30NB2F2 IO30PB2F2 IO31NB2F2 IO31PB2F2 IO33NB2F2 IO33PB2F2 IO34NB2F2 IO34PB2F2 IO35NB2F2 IO35PB2F2 IO36NB2F2 IO36PB2F2 IO37NB2F2 IO37PB2F2 IO38NB2F2 IO38PB2F2 IO39NB2F2 IO39PB2F2 IO41NB2F2 IO41PB2F2 IO42NB2F2 IO42PB2F2 IO43NB2F2 IO43PB2F2 IO44NB2F2 IO44PB2F2 Bank 3 IO45NB3F3 IO45PB3F3 IO46NB3F3 217 218 219 261 262 259 260 255 256 249 250 253 254 247 248 243 244 241 242 237 238 235 236 231 232 229 230 225 226 223 224 Pin # 271 272 269 270
352-Pin CQFP AX250 Function IO46PB3F3 IO47NB3F3 IO47PB3F3 IO48NB3F3 IO48PB3F3 IO49NB3F3 IO49PB3F3 IO51NB3F3 IO51PB3F3 IO52NB3F3 IO52PB3F3 IO53NB3F3 IO53PB3F3 IO54NB3F3 IO54PB3F3 IO55NB3F3 IO55PB3F3 IO56NB3F3 IO56PB3F3 IO57NB3F3 IO57PB3F3 IO59NB3F3 IO59PB3F3 IO60NB3F3 IO60PB3F3 IO61NB3F3 IO61PB3F3 Bank 4 IO62NB4F4 IO62PB4F4 IO64NB4F4 IO64PB4F4 IO65NB4F4 IO65PB4F4 IO66NB4F4 IO66PB4F4 IO67NB4F4 172 173 166 167 170 171 164 165 160 Pin # 220 213 214 211 212 207 208 205 206 201 202 199 200 195 196 193 194 187 188 189 190 183 184 181 182 179 180
v2.7
3-89
Axcelerator Family FPGAs
352-Pin CQFP AX250 Function IO67PB4F4 IO68NB4F4 IO68PB4F4 IO70NB4F4 IO70PB4F4 IO72NB4F4 IO72PB4F4 IO73NB4F4 IO73PB4F4 IO74NB4F4/CLKEN IO74PB4F4/CLKEP IO75NB4F4/CLKFN IO75PB4F4/CLKFP Bank 5 IO76NB5F5/CLKGN IO76PB5F5/CLKGP IO77NB5F5/CLKHN IO77PB5F5/CLKHP IO78NB5F5 IO78PB5F5 IO79NB5F5 IO79PB5F5 IO80NB5F5 IO80PB5F5 IO82NB5F5 IO82PB5F5 IO84NB5F5 IO84PB5F5 IO85NB5F5 IO85PB5F5 IO86NB5F5 IO86PB5F5 IO87NB5F5 IO87PB5F5 IO89NB5F5 IO89PB5F5 Bank 6 128 129 122 123 112 113 118 119 110 111 106 107 100 101 104 105 98 99 94 95 92 93 Pin # 161 158 159 154 155 152 153 146 147 142 143 136 137
352-Pin CQFP AX250 Function IO90PB6F6 IO91NB6F6 IO91PB6F6 IO92NB6F6 IO92PB6F6 IO93NB6F6 IO93PB6F6 IO95NB6F6 IO95PB6F6 IO96NB6F6 IO96PB6F6 IO97NB6F6 IO97PB6F6 IO98NB6F6 IO98PB6F6 IO99NB6F6 IO99PB6F6 IO100NB6F6 IO100PB6F6 IO101NB6F6 IO101PB6F6 IO103NB6F6 IO103PB6F6 IO104NB6F6 IO104PB6F6 IO105NB6F6 IO105PB6F6 IO106NB6F6 IO106PB6F6 Bank 7 IO107NB7F7 IO107PB7F7 IO108NB7F7 IO108PB7F7 IO109NB7F7 IO109PB7F7 IO110NB7F7 40 41 42 43 36 37 34 Pin # 86 84 85 78 79 82 83 76 77 72 73 70 71 66 67 64 65 60 61 58 59 54 55 52 53 48 49 46 47
352-Pin CQFP AX250 Function IO110PB7F7 IO111NB7F7 IO111PB7F7 IO113NB7F7 IO113PB7F7 IO114NB7F7 IO114PB7F7 IO115NB7F7 IO115PB7F7 IO116NB7F7 IO116PB7F7 IO117NB7F7 IO117PB7F7 IO118NB7F7 IO118PB7F7 IO119NB7F7 IO119PB7F7 IO121NB7F7 IO121PB7F7 IO123NB7F7 IO123PB7F7 Dedicated I/O GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 1 9 15 21 27 33 39 45 51 57 63 69 75 81 88 Pin # 35 30 31 28 29 24 25 22 23 18 19 16 17 12 13 10 11 6 7 4 5
3 -9 0
v2.7
Axcelerator Family FPGAs
352-Pin CQFP AX250 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin # 89 97 103 109 115 121 133 145 151 157 163 169 176 177 186 192 198 204 210 216 222 228 234 240 246 252 258 264 265 274 280 286 292 298 310 322 330
352-Pin CQFP AX250 Function GND GND GND GND NC NC NC NC NC NC NC NC NC NC NC NC PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA Pin # 334 340 345 352 91 117 130 131 148 174 268 294 307 308 327 328 312 311 135 134 349 348 347 350 351 3 14 32 56 74 87 102 114 150 162 175 191
352-Pin CQFP AX250 Function VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 Pin # 209 233 251 263 279 291 329 339 2 44 90 116 132 149 178 221 266 293 309 346 321 333 344 273 285 297 227 239 245 257 185 197 203 215 144 156 168
v2.7
3-91
Axcelerator Family FPGAs
352-Pin CQFP AX250 Function VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin # 96 108 120 50 62 68 80 8 20 26 38 317 315 303 301 140 138 126 124 318 316 304 302 141 139 127 125 267
352-Pin CQFP AX500 Function Bank 0 IO00PB0F0 IO03NB0F0 IO03PB0F0 IO05NB0F0 IO05PB0F0 IO07NB0F0 IO07PB0F0 IO09NB0F0 IO09PB0F0 IO15NB0F1 IO15PB0F1 IO17NB0F1 IO17PB0F1 IO19NB0F1/HCLKAN IO19PB0F1/HCLKAP IO20NB0F1/HCLKBN IO20PB0F1/HCLKBP Bank 1 IO21NB1F2/HCLKCN IO21PB1F2/HCLKCP IO22NB1F2/HCLKDN IO22PB1F2/HCLKDP IO23NB1F2 IO23PB1F2 IO24NB1F2 IO24PB1F2 IO25NB1F2 IO25PB1F2 IO27NB1F2 IO27PB1F2 IO29NB1F2 IO29PB1F2 IO31NB1F2 IO31PB1F2 IO35NB1F3 IO35PB1F3 305 306 299 300 289 290 295 296 287 288 283 284 281 282 277 278 275 276 343 341 342 337 338 335 336 331 332 325 326 323 324 319 320 313 314 Pin #
352-Pin CQFP AX500 Function IO37NB1F3 IO37PB1F3 IO41NB1F3 IO41PB1F3 Bank 2 IO43NB2F4 IO43PB2F4 IO45NB2F4 IO45PB2F4 IO47NB2F4 IO47PB2F4 IO49NB2F4 IO49PB2F4 IO50NB2F4 IO50PB2F4 IO51NB2F4 IO51PB2F4 IO53NB2F5 IO53PB2F5 IO54NB2F5 IO54PB2F5 IO55NB2F5 IO55PB2F5 IO57NB2F5 IO57PB2F5 IO58NB2F5 IO58PB2F5 IO59NB2F5 IO59PB2F5 IO61NB2F5 IO61PB2F5 IO62NB2F5 IO62PB2F5 Bank 3 IO63NB3F6 IO63PB3F6 IO64NB3F6 217 218 219 261 262 259 260 255 256 253 254 247 248 249 250 243 244 241 242 237 238 235 236 231 232 229 230 225 226 223 224 Pin # 271 272 269 270
3 -9 2
v2.7
Axcelerator Family FPGAs
352-Pin CQFP AX500 Function IO64PB3F6 IO65NB3F6 IO65PB3F6 IO67NB3F6 IO67PB3F6 IO68NB3F6 IO68PB3F6 IO69NB3F6 IO69PB3F6 IO71NB3F6 IO71PB3F6 IO73NB3F6 IO73PB3F6 IO75NB3F7 IO75PB3F7 IO76NB3F7 IO76PB3F7 IO77NB3F7 IO77PB3F7 IO79NB3F7 IO79PB3F7 IO80NB3F7 IO80PB3F7 IO81NB3F7 IO81PB3F7 IO83NB3F7 IO83PB3F7 Bank 4 IO85NB4F8 IO85PB4F8 IO87NB4F8 IO87PB4F8 IO89NB4F8 IO89PB4F8 IO94NB4F9 IO94PB4F9 IO95NB4F9 172 173 170 171 166 167 164 165 160 Pin # 220 213 214 207 208 211 212 205 206 201 202 199 200 193 194 195 196 189 190 187 188 183 184 181 182 179 180
352-Pin CQFP AX500 Function IO95PB4F9 IO97NB4F9 IO97PB4F9 IO99NB4F9 IO99PB4F9 IO100NB4F9 IO100PB4F9 IO101NB4F9 IO101PB4F9 IO103NB4F9/CLKEN IO103PB4F9/CLKEP IO104NB4F9/CLKFN IO104PB4F9/CLKFP Bank 5 IO105NB5F10/CLKGN IO105PB5F10/CLKGP IO106NB5F10/CLKHN IO106PB5F10/CLKHP IO107NB5F10 IO107PB5F10 IO114NB5F11 IO114PB5F11 IO115NB5F11 IO115PB5F11 IO116NB5F11 IO116PB5F11 IO117NB5F11 IO117PB5F11 IO119NB5F11 IO119PB5F11 IO121NB5F11 IO121PB5F11 IO123NB5F11 IO123PB5F11 IO125NB5F11 IO125PB5F11 Bank 6 128 129 122 123 118 119 112 113 110 111 106 107 104 105 100 101 98 99 94 95 92 93 Pin # 161 158 159 154 155 146 147 152 153 142 143 136 137
352-Pin CQFP AX500 Function IO126PB6F12 IO127NB6F12 IO127PB6F12 IO129NB6F12 IO129PB6F12 IO131NB6F12 IO131PB6F12 IO133NB6F12 IO133PB6F12 IO134NB6F12 IO134PB6F12 IO135NB6F12 IO135PB6F12 IO137NB6F13 IO137PB6F13 IO138NB6F13 IO138PB6F13 IO139NB6F13 IO139PB6F13 IO141NB6F13 IO141PB6F13 IO142NB6F13 IO142PB6F13 IO143NB6F13 IO143PB6F13 IO145NB6F13 IO145PB6F13 IO146NB6F13 IO146PB6F13 Bank 7 IO147NB7F14 IO147PB7F14 IO148NB7F14 IO148PB7F14 IO149NB7F14 IO149PB7F14 IO151NB7F14 40 41 42 43 36 37 30 Pin # 86 84 85 82 83 78 79 76 77 72 73 70 71 66 67 64 65 60 61 54 55 58 59 52 53 48 49 46 47
v2.7
3-93
Axcelerator Family FPGAs
352-Pin CQFP AX500 Function IO151PB7F14 IO152NB7F14 IO152PB7F14 IO153NB7F14 IO153PB7F14 IO155NB7F14 IO155PB7F14 IO157NB7F14 IO157PB7F14 IO159NB7F15 IO159PB7F15 IO160NB7F15 IO160PB7F15 IO161NB7F15 IO161PB7F15 IO163NB7F15 IO163PB7F15 IO165NB7F15 IO165PB7F15 IO167NB7F15 IO167PB7F15 Dedicated I/O GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 1 9 15 21 27 33 39 45 51 57 63 69 75 81 88 Pin # 31 34 35 28 29 24 25 22 23 16 17 18 19 12 13 10 11 6 7 4 5
352-Pin CQFP AX500 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin # 89 97 103 109 115 121 133 145 151 157 163 169 176 177 186 192 198 204 210 216 222 228 234 240 246 252 258 264 265 274 280 286 292 298 310 322 330
352-Pin CQFP AX500 Function GND GND GND GND/LP NC NC NC NC NC NC NC NC NC NC NC NC PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA Pin # 334 340 345 352 91 117 130 131 148 174 268 294 307 308 327 328 312 311 135 134 349 348 347 350 351 3 14 32 56 74 87 102 114 150 162 175 191
3 -9 4
v2.7
Axcelerator Family FPGAs
352-Pin CQFP AX500 Function VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 Pin # 209 233 251 263 279 291 329 339 2 44 90 116 132 149 178 221 266 293 309 346 321 333 344 273 285 297 227 239 245 257 185 197 203 215 144 156 168
352-Pin CQFP AX500 Function VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin # 96 108 120 50 62 68 80 8 20 26 38 317 315 303 301 140 138 126 124 318 316 304 302 141 139 127 125 267
352-Pin CQFP AX1000 Function Bank 0 IO02NB0F0 IO02PB0F0 IO03PB0F0 IO04NB0F0 IO04PB0F0 IO08NB0F0 IO08PB0F0 IO09NB0F0 IO09PB0F0 IO24NB0F2 IO24PB0F2 IO25NB0F2 IO25PB0F2 IO30NB0F2/HCLKAN IO30PB0F2/HCLKAP IO31NB0F2/HCLKBN IO31PB0F2/HCLKBP Bank 1 IO32NB1F3/HCLKCN IO32PB1F3/HCLKCP IO33NB1F3/HCLKDN IO33PB1F3/HCLKDP IO38NB1F3 IO38PB1F3 IO54NB1F5 IO54PB1F5 IO55NB1F5 IO55PB1F5 IO56NB1F5 IO56PB1F5 IO57NB1F5 IO57PB1F5 IO59NB1F5 IO59PB1F5 IO60NB1F5 IO60PB1F5 305 306 299 300 295 296 287 288 289 290 281 282 283 284 277 278 275 276 341 342 343 337 338 331 332 335 336 325 326 323 324 319 320 313 314 Pin #
v2.7
3-95
Axcelerator Family FPGAs
352-Pin CQFP AX1000 Function IO61NB1F5 IO61PB1F5 IO63NB1F5 IO63PB1F5 Bank 2 IO64NB2F6 IO64PB2F6 IO67NB2F6 IO67PB2F6 IO68NB2F6 IO68PB2F6 IO69NB2F6 IO69PB2F6 IO74NB2F7 IO74PB2F7 IO75NB2F7 IO75PB2F7 IO76NB2F7 IO76PB2F7 IO77NB2F7 IO77PB2F7 IO78NB2F7 IO78PB2F7 IO79NB2F7 IO79PB2F7 IO82NB2F7 IO82PB2F7 IO83NB2F7 IO83PB2F7 IO94NB2F8 IO94PB2F8 IO95NB2F8 IO95PB2F8 Bank 3 IO96NB3F9 IO96PB3F9 IO97NB3F9 217 218 219 259 260 261 262 255 256 253 254 249 250 247 248 243 244 241 242 237 238 235 236 231 232 229 230 225 226 223 224 Pin # 271 272 269 270
352-Pin CQFP AX1000 Function IO97PB3F9 IO99NB3F9 IO99PB3F9 IO108NB3F10 IO108PB3F10 IO109NB3F10 IO109PB3F10 IO111NB3F10 IO111PB3F10 IO112NB3F10 IO112PB3F10 IO113NB3F10 IO113PB3F10 IO115NB3F10 IO115PB3F10 IO116NB3F10 IO116PB3F10 IO117NB3F10 IO117PB3F10 IO124NB3F11 IO124PB3F11 IO125NB3F11 IO125PB3F11 IO127NB3F11 IO127PB3F11 IO128NB3F11 IO128PB3F11 Bank 4 IO130NB4F12 IO130PB4F12 IO131NB4F12 IO131PB4F12 IO132NB4F12 IO132PB4F12 IO133NB4F12 IO133PB4F12 IO134NB4F12 172 173 170 171 166 167 164 165 160 Pin # 220 213 214 211 212 207 208 205 206 199 200 201 202 195 196 193 194 189 190 183 184 187 188 181 182 179 180
352-Pin CQFP AX1000 Function IO134PB4F12 IO136NB4F12 IO136PB4F12 IO137NB4F12 IO137PB4F12 IO138NB4F12 IO138PB4F12 IO153NB4F14 IO153PB4F14 IO159NB4F14/CLKEN IO159PB4F14/CLKEP IO160NB4F14/CLKFN IO160PB4F14/CLKFP Bank 5 IO161NB5F15/CLKGN IO161PB5F15/CLKGP IO162NB5F15/CLKHN IO162PB5F15/CLKHP IO167NB5F15 IO167PB5F15 IO183NB5F17 IO183PB5F17 IO184NB5F17 IO184PB5F17 IO185NB5F17 IO185PB5F17 IO186NB5F17 IO186PB5F17 IO187NB5F17 IO187PB5F17 IO188NB5F17 IO188PB5F17 IO190NB5F17 IO190PB5F17 IO192NB5F17 IO192PB5F17 Bank 6 128 129 122 123 118 119 110 111 112 113 104 105 106 107 98 99 100 101 94 95 92 93 Pin # 161 158 159 154 155 152 153 146 147 142 143 136 137
3 -9 6
v2.7
Axcelerator Family FPGAs
352-Pin CQFP AX1000 Function IO193PB6F18 IO194NB6F18 IO194PB6F18 IO196NB6F18 IO196PB6F18 IO197NB6F18 IO197PB6F18 IO198NB6F18 IO198PB6F18 IO203NB6F19 IO203PB6F19 IO204NB6F19 IO204PB6F19 IO205NB6F19 IO205PB6F19 IO206NB6F19 IO206PB6F19 IO207NB6F19 IO207PB6F19 IO208NB6F19 IO208PB6F19 IO211NB6F19 IO211PB6F19 IO212NB6F19 IO212PB6F19 IO223NB6F20 IO223PB6F20 IO224NB6F20 IO224PB6F20 Bank 7 IO225NB7F21 IO225PB7F21 IO226NB7F21 IO226PB7F21 IO237NB7F22 IO237PB7F22 IO238NB7F22 40 41 42 43 34 35 36 Pin # 86 84 85 78 79 82 83 76 77 72 73 70 71 66 67 64 65 60 61 58 59 54 55 52 53 48 49 46 47
352-Pin CQFP AX1000 Function IO238PB7F22 IO240NB7F22 IO240PB7F22 IO241NB7F22 IO241PB7F22 IO242NB7F22 IO242PB7F22 IO244NB7F22 IO244PB7F22 IO245NB7F22 IO245PB7F22 IO246NB7F22 IO246PB7F22 IO249NB7F23 IO249PB7F23 IO250NB7F23 IO250PB7F23 IO256NB7F23 IO256PB7F23 IO257NB7F23 IO257PB7F23 Dedicated I/O GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 1 9 15 21 27 33 39 45 51 57 63 69 75 81 88 Pin # 37 30 31 28 29 24 25 22 23 18 19 16 17 12 13 10 11 4 5 6 7
352-Pin CQFP AX1000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin # 89 97 103 109 115 121 133 145 151 157 163 169 176 177 186 192 198 204 210 216 222 228 234 240 246 252 258 264 265 274 280 286 292 298 310 322 330
v2.7
3-97
Axcelerator Family FPGAs
352-Pin CQFP AX1000 Function GND GND GND GND NC NC NC NC NC NC NC PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA Pin # 334 340 345 352 91 130 131 174 268 307 308 312 311 135 134 349 348 347 350 351 3 14 32 56 74 87 102 114 150 162 175 191 209 233 251 263 279
352-Pin CQFP AX1000 Function VCCA VCCA VCCA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 Pin # 291 329 339 2 44 90 116 117 132 148 149 178 221 266 293 294 309 327 328 346 321 333 344 273 285 297 227 239 245 257 185 197 203 215 144 156 168
352-Pin CQFP AX1000 Function VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin # 96 108 120 50 62 68 80 8 20 26 38 317 315 303 301 140 138 126 124 318 316 304 302 141 139 127 125 267
3 -9 8
v2.7
Axcelerator Family FPGAs
352-Pin CQFP AX2000 Function Bank 0 IO01NB0F0 IO01PB0F0 IO02PB0F0 IO04NB0F0 IO04PB0F0 IO05NB0F0 IO05PB0F0 IO08NB0F0 IO08PB0F0 IO37NB0F3 IO37PB0F3 IO38NB0F3 IO38PB0F3 IO41NB0F3/HCLKAN IO41PB0F3/HCLKAP IO42NB0F3/HCLKBN IO42PB0F3/HCLKBP Bank 1 IO43NB1F4/HCLKCN IO43PB1F4/HCLKCP IO44NB1F4/HCLKDN IO44PB1F4/HCLKDP IO48NB1F4 IO48PB1F4 IO65NB1F6 IO65PB1F6 IO66NB1F6 IO66PB1F6 IO68NB1F6 IO68PB1F6 IO69NB1F6 IO69PB1F6 IO70NB1F6 IO70PB1F6 IO71NB1F6 IO71PB1F6 IO73NB1F6 IO73PB1F6 IO74NB1F6 IO74PB1F6 305 306 299 300 295 296 283 284 289 290 287 288 275 276 281 282 277 278 269 270 271 272 341 342 343 337 338 335 336 331 332 325 326 323 324 319 320 313 314 Pin Number
352-Pin CQFP AX2000 Function Bank 2 IO87NB2F8 IO87PB2F8 IO88NB2F8 IO88PB2F8 IO89NB2F8 IO89PB2F8 IO91NB2F8 IO91PB2F8 IO99NB2F9 IO99PB2F9 IO100NB2F9 IO100PB2F9 IO107NB2F10 IO107PB2F10 IO110NB2F10 IO110PB2F10 IO111NB2F10 IO111PB2F10 IO112NB2F10 IO112PB2F10 IO113NB2F10 IO113PB2F10 IO114NB2F10 IO114PB2F10 IO115NB2F10 IO115PB2F10 IO117NB2F10 IO117PB2F10 Bank 3 IO129NB3F12 IO129PB3F12 IO132NB3F12 IO132PB3F12 IO137NB3F12 IO137PB3F12 IO139NB3F13 IO139PB3F13 IO141NB3F13 IO141PB3F13 IO142NB3F13 219 220 217 218 213 214 211 212 205 206 207 261 262 255 256 259 260 253 254 249 250 247 248 243 244 241 242 237 238 235 236 231 232 229 230 225 226 223 224 Pin Number
352-Pin CQFP AX2000 Function IO142PB3F13 IO145NB3F13 IO145PB3F13 IO146NB3F13 IO146PB3F13 IO147NB3F13 IO147PB3F13 IO148NB3F13 IO148PB3F13 IO149NB3F13 IO149PB3F13 IO161NB3F15 IO161PB3F15 IO163NB3F15 IO163PB3F15 IO165NB3F15 IO165PB3F15 IO167NB3F15 IO167PB3F15 Bank 4 IO181NB4F17 IO181PB4F17 IO182NB4F17 IO182PB4F17 IO183NB4F17 IO183PB4F17 IO184NB4F17 IO184PB4F17 IO185NB4F17 IO185PB4F17 IO190NB4F17 IO190PB4F17 IO191NB4F17 IO191PB4F17 IO192NB4F17 IO192PB4F17 IO207NB4F19 IO207PB4F19 IO212NB4F19/CLKEN IO212PB4F19/CLKEP IO213NB4F19/CLKFN 172 173 170 171 166 167 164 165 160 161 158 159 154 155 152 153 146 147 142 143 136 Pin Number 208 199 200 201 202 193 194 195 196 189 190 183 184 187 188 181 182 179 180
v2.7
3-99
Axcelerator Family FPGAs
352-Pin CQFP AX2000 Function IO213PB4F19/CLKFP Bank 5 IO214NB5F20/CLKGN IO214PB5F20/CLKGP IO215NB5F20/CLKHN IO215PB5F20/CLKHP IO217NB5F20 IO217PB5F20 IO236NB5F22 IO236PB5F22 IO237NB5F22 IO237PB5F22 IO238NB5F22 IO238PB5F22 IO239NB5F22 IO239PB5F22 IO240NB5F22 IO240PB5F22 IO242NB5F22 IO242PB5F22 IO243NB5F22 IO243PB5F22 IO244NB5F22 IO244PB5F22 Bank 6 IO257PB6F24 IO258NB6F24 IO258PB6F24 IO261NB6F24 IO261PB6F24 IO262NB6F24 IO262PB6F24 IO265NB6F24 IO265PB6F24 IO279NB6F26 IO279PB6F26 IO280NB6F26 IO280PB6F26 IO281NB6F26 IO281PB6F26 IO282NB6F26 86 84 85 82 83 78 79 76 77 72 73 70 71 66 67 64 128 129 122 123 118 119 110 111 112 113 104 105 106 107 100 101 94 95 98 99 92 93 Pin Number 137
352-Pin CQFP AX2000 Function IO282PB6F26 IO284NB6F26 IO284PB6F26 IO285NB6F26 IO285PB6F26 IO286NB6F26 IO286PB6F26 IO287NB6F26 IO287PB6F26 IO294NB6F27 IO294PB6F27 IO296NB6F27 IO296PB6F27 Bank 7 IO300NB7F28 IO300PB7F28 IO303NB7F28 IO303PB7F28 IO310NB7F29 IO310PB7F29 IO311NB7F29 IO311PB7F29 IO312NB7F29 IO312PB7F29 IO315NB7F29 IO315PB7F29 IO316NB7F29 IO316PB7F29 IO317NB7F29 IO317PB7F29 IO318NB7F29 IO318PB7F29 IO320NB7F29 IO320PB7F29 IO334NB7F31 IO334PB7F31 IO335NB7F31 IO335PB7F31 IO338NB7F31 IO338PB7F31 IO341NB7F31 42 43 40 41 34 35 36 37 28 29 30 31 22 23 24 25 18 19 16 17 10 11 12 13 6 7 4 Pin Number 65 60 61 58 59 54 55 52 53 48 49 46 47
352-Pin CQFP AX2000 Function IO341PB7F31 Dedicated I/O GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 1 9 15 21 27 33 39 45 51 57 63 69 75 81 88 89 97 103 109 115 121 133 145 151 157 163 169 176 177 186 192 198 204 210 216 222 228 234 240 Pin Number 5
3 -1 0 0
v2.7
Axcelerator Family FPGAs
352-Pin CQFP AX2000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA Pin Number 246 252 258 264 265 274 280 286 292 298 310 322 330 334 340 345 352 312 311 135 134 349 348 347 350 351 3 14 32 56 74 87 102 114 150 162 175 191 209 233 251
352-Pin CQFP AX2000 Function VCCA VCCA VCCA VCCA VCCA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 Pin Number 263 279 291 329 339 2 44 90 91 116 117 130 131 132 148 149 174 178 221 266 268 293 294 307 308 309 327 328 346 321 333 344 273 285 297 227 239 245 257 185 197
352-Pin CQFP AX2000 Function VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number 203 215 144 156 168 96 108 120 50 62 68 80 8 20 26 38 317 315 303 301 140 138 126 124 318 316 304 302 141 139 127 125 267
v2.7
3-101
Axcelerator Family FPGAs
624-Pin CCGA
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 54321 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE
Figure 3-12 * 624-Pin CCGA (Bottom View)
Note
For Package Manufacturing and Environmental information, visit Resource center at http://www.actel.com/products/rescenter/package/index.html.
3 -1 0 2
v2.7
Axcelerator Family FPGAs
624-Pin CCGA AX1000 Function Bank 0 IO00NB0F0 IO00PB0F0 IO02NB0F0 IO02PB0F0 IO04NB0F0 IO04PB0F0 IO06NB0F0 IO06PB0F0 IO07PB0F0 IO08NB0F0 IO08PB0F0 IO09PB0F0 IO10NB0F0 IO10PB0F0 IO11NB0F0 IO11PB0F0 IO12NB0F1 IO12PB0F1 IO13NB0F1 IO13PB0F1 IO14NB0F1 IO14PB0F1 IO15PB0F1 IO16NB0F1 IO16PB0F1 IO17NB0F1 IO17PB0F1 IO18NB0F1 IO18PB0F1 IO20NB0F1 IO20PB0F1 IO21NB0F1 IO21PB0F1 IO22NB0F2 IO22PB0F2 IO23NB0F2 F8 F7 G7 G6 E9 D8 G9 G8 B6 F10 F9 C7 H8 H7 D10 D9 B5 B4 A7 A6 C9 C8 B7 A5 A4 A9 B9 D12 D11 B11 B10 A11 A10 H10 H9 E11 Pin Number
624-Pin CCGA AX1000 Function IO23PB0F2 IO24NB0F2 IO24PB0F2 IO25PB0F2 IO26NB0F2 IO26PB0F2 IO27NB0F2 IO27PB0F2 IO28NB0F2 IO28PB0F2 IO29NB0F2 IO29PB0F2 IO30NB0F2/HCLKAN IO30PB0F2/HCLKAP IO31NB0F2/HCLKBN IO31PB0F2/HCLKBP Bank 1 IO32NB1F3/HCLKCN IO32PB1F3/HCLKCP IO33NB1F3/HCLKDN IO33PB1F3/HCLKDP IO34NB1F3 IO34PB1F3 IO35NB1F3 IO35PB1F3 IO36NB1F3 IO36PB1F3 IO37NB1F3 IO38NB1F3 IO38PB1F3 IO39NB1F3 IO39PB1F3 IO40NB1F3 IO40PB1F3 IO41NB1F4 IO42NB1F4 IO42PB1F4 G15 G14 B14 B13 G16 H16 C17 B18 H18 H15 H13 E15 F15 D14 C14 D16 D15 F16 G21 G20 Pin Number F11 D7 E7 B12 H11 G11 C11 B8 J13 K13 J8 J7 G13 G12 C13 C12
624-Pin CCGA AX1000 Function IO43NB1F4 IO43PB1F4 IO44NB1F4 IO44PB1F4 IO45NB1F4 IO45PB1F4 IO46NB1F4 IO46PB1F4 IO47NB1F4 IO48NB1F4 IO48PB1F4 IO49NB1F4 IO49PB1F4 IO50NB1F4 IO50PB1F4 IO51NB1F4 IO51PB1F4 IO52NB1F4 IO52PB1F4 IO53NB1F4 IO53PB1F4 IO54NB1F5 IO54PB1F5 IO55NB1F5 IO55PB1F5 IO56NB1F5 IO56PB1F5 IO58NB1F5 IO58PB1F5 IO60NB1F5 IO60PB1F5 IO62NB1F5 IO62PB1F5 IO63NB1F5 IO63PB1F5 Bank 2 IO64NB2F6 M17 Pin Number A16 A15 A20 A19 B17 B16 G17 H17 A17 C19 C18 B20 B19 H20 H19 A22 A21 C21 C20 B22 B21 J18 J19 D18 D17 F20 F19 E17 F17 D20 D19 E18 F18 G19 G18
v2.7
3-103
Axcelerator Family FPGAs
624-Pin CCGA AX1000 Function IO64PB2F6 IO65NB2F6 IO65PB2F6 IO66NB2F6 IO66PB2F6 IO67NB2F6 IO67PB2F6 IO68NB2F6 IO68PB2F6 IO70NB2F6 IO70PB2F6 IO71NB2F6 IO71PB2F6 IO72NB2F6 IO72PB2F6 IO74NB2F7 IO74PB2F7 IO75NB2F7 IO75PB2F7 IO76NB2F7 IO76PB2F7 IO77NB2F7 IO77PB2F7 IO78NB2F7 IO78PB2F7 IO79NB2F7 IO79PB2F7 IO80NB2F7 IO80PB2F7 IO82NB2F7 IO82PB2F7 IO83NB2F7 IO83PB2F7 IO84NB2F7 IO84PB2F7 IO86NB2F8 IO86PB2F8 Pin Number G22 J21 J20 L23 K20 F23 E23 L18 K18 E24 D24 H23 G23 L19 K19 J22 H22 N23 M23 N17 N16 L22 K22 M19 M18 N19 N18 L21 L20 P18 P17 N22 M22 M20 M21 E25 D25
624-Pin CCGA AX1000 Function IO87NB2F8 IO87PB2F8 IO88NB2F8 IO88PB2F8 IO89NB2F8 IO90NB2F8 IO90PB2F8 IO91NB2F8 IO91PB2F8 IO92NB2F8 IO92PB2F8 IO93PB2F8 IO94NB2F8 IO94PB2F8 IO95NB2F8 IO95PB2F8 Bank 3 IO96NB3F9 IO96PB3F9 IO97NB3F9 IO97PB3F9 IO98NB3F9 IO98PB3F9 IO99NB3F9 IO100NB3F9 IO100PB3F9 IO101NB3F9 IO101PB3F9 IO102NB3F9 IO102PB3F9 IO104NB3F9 IO104PB3F9 IO105NB3F9 IO105PB3F9 IO106NB3F9 IO106PB3F9 IO107NB3F10 T18 R18 N20 P24 P20 P19 P21 T22 W24 R22 P22 U19 T19 V20 U20 R23 P23 R19 R20 AB24 Pin Number L24 K24 G24 F24 J25 G25 F25 L25 K25 J24 H24 J23 N24 M24 N25 M25
624-Pin CCGA AX1000 Function IO108NB3F10 IO108PB3F10 IO109NB3F10 IO109PB3F10 IO110NB3F10 IO110PB3F10 IO112NB3F10 IO112PB3F10 IO113NB3F10 IO113PB3F10 IO114NB3F10 IO114PB3F10 IO116NB3F10 IO116PB3F10 IO117NB3F10 IO117PB3F10 IO118NB3F11 IO118PB3F11 IO120NB3F11 IO120PB3F11 IO122NB3F11 IO122PB3F11 IO124NB3F11 IO124PB3F11 IO126NB3F11 IO126PB3F11 IO128NB3F11 IO128PB3F11 Bank 4 IO129NB4F12 IO129PB4F12 IO131NB4F12 IO131PB4F12 IO133NB4F12 IO133PB4F12 IO135NB4F12 IO135PB4F12 W20 Y20 V19 W19 Y18 Y19 W18 V18 Pin Number R25 P25 U25 T25 U24 U23 T24 R24 Y25 W25 V23 V24 AA24 Y24 AB25 AA25 T20 R21 W22 W23 V22 U22 Y23 AA23 V21 U21 Y22 Y21
3 -1 0 4
v2.7
Axcelerator Family FPGAs
624-Pin CCGA AX1000 Function IO137NB4F12 IO137PB4F12 IO138NB4F12 IO138PB4F12 IO139NB4F13 IO139PB4F13 IO140NB4F13 IO140PB4F13 IO141NB4F13 IO141PB4F13 IO142NB4F13 IO142PB4F13 IO143NB4F13 IO143PB4F13 IO144PB4F13 IO145NB4F13 IO145PB4F13 IO146NB4F13 IO146PB4F13 IO147NB4F13 IO147PB4F13 IO148PB4F13 IO149NB4F13 IO149PB4F13 IO150NB4F13 IO150PB4F13 IO151NB4F13 IO151PB4F13 IO152NB4F14 IO152PB4F14 IO153NB4F14 IO153PB4F14 IO155NB4F14 IO155PB4F14 IO156NB4F14 IO156PB4F14 IO157NB4F14 Pin Number Y17 AA17 AB19 AB18 AA19 U18 AC20 AC21 AD17 AD18 AD21 AD22 AB17 AC17 AE22 AE15 AE16 AD19 AD20 AD15 AD16 AE21 AD14 AC14 AE19 AE20 V17 W17 AB16 W16 Y15 Y16 V15 V16 AB14 AB15 AE14
624-Pin CCGA AX1000 Function IO157PB4F14 IO158NB4F14 IO158PB4F14 IO159NB4F14/CLKEN IO159PB4F14/CLKEP IO160NB4F14/CLKFN IO160PB4F14/CLKFP Bank 5 IO161NB5F15/CLKGN IO161PB5F15/CLKGP IO162NB5F15/CLKHN IO162PB5F15/CLKHP IO163NB5F15 IO163PB5F15 IO164NB5F15 IO164PB5F15 IO165NB5F15 IO165PB5F15 IO167NB5F15 IO167PB5F15 IO168NB5F15 IO168PB5F15 IO169NB5F15 IO169PB5F15 IO171NB5F16 IO171PB5F16 IO172NB5F16 IO172PB5F16 IO173NB5F16 IO173PB5F16 IO174NB5F16 IO174PB5F16 IO175NB5F16 IO175PB5F16 IO177NB5F16 IO177PB5F16 IO178NB5F16 W13 Y13 AC12 AD12 V9 V10 V11 T13 U13 V13 W11 W12 AB6 AA6 V8 V7 W8 W9 AB8 AC8 AA11 Y11 AB10 AB11 AC9 AE9 AA8 Y8 Y6 Pin Number AC18 AC15 AC19 W14 W15 AC13 AD13
624-Pin CCGA AX1000 Function IO178PB5F16 IO179NB5F16 IO179PB5F16 IO180NB5F16 IO180PB5F16 IO181NB5F17 IO181PB5F17 IO182NB5F17 IO182PB5F17 IO183NB5F17 IO183PB5F17 IO184NB5F17 IO185NB5F17 IO185PB5F17 IO186NB5F17 IO186PB5F17 IO187NB5F17 IO187PB5F17 IO188NB5F17 IO189NB5F17 IO189PB5F17 IO191NB5F17 IO191PB5F17 IO192NB5F17 IO192PB5F17 Bank 6 IO193NB6F18 IO193PB6F18 IO194NB6F18 IO194PB6F18 IO195NB6F18 IO195PB6F18 IO197NB6F18 IO197PB6F18 IO198NB6F18 IO199NB6F18 IO199PB6F18 U6 U5 Y3 AA3 V6 W4 R5 U3 P6 Y5 W5 Pin Number W6 Y10 W10 Y7 W7 AD9 AD10 AE10 AE11 AD7 AD8 AB9 AE6 AE7 AE4 AE5 AA9 Y9 U8 AD5 AD6 AC5 AC6 AB7 AC7
v2.7
3-105
Axcelerator Family FPGAs
624-Pin CCGA AX1000 Function IO200NB6F18 IO200PB6F18 IO201NB6F18 IO201PB6F18 IO202NB6F18 IO203NB6F19 IO203PB6F19 IO204NB6F19 IO204PB6F19 IO205NB6F19 IO205PB6F19 IO206NB6F19 IO206PB6F19 IO207NB6F19 IO207PB6F19 IO208NB6F19 IO208PB6F19 IO209NB6F19 IO209PB6F19 IO210NB6F19 IO211NB6F19 IO211PB6F19 IO212NB6F19 IO212PB6F19 IO213NB6F19 IO213PB6F19 IO215NB6F20 IO215PB6F20 IO216NB6F20 IO216PB6F20 IO217NB6F20 IO217PB6F20 IO219NB6F20 IO219PB6F20 IO220NB6F20 IO220PB6F20 IO221NB6F20 Pin Number V3 W3 T7 U7 V2 W2 Y2 AA1 AB1 R6 T6 W1 Y1 T2 U2 T1 U1 AA2 AB2 P5 M1 N1 P1 R1 R8 T8 U4 V4 P8 R3 P7 R7 R4 T4 P2 R2 N4
624-Pin CCGA AX1000 Function IO221PB6F20 IO223NB6F20 IO223PB6F20 IO224NB6F20 IO224PB6F20 Bank 7 IO225NB7F21 IO225PB7F21 IO226PB7F21 IO227NB7F21 IO227PB7F21 IO229NB7F21 IO229PB7F21 IO230NB7F21 IO230PB7F21 IO231NB7F21 IO231PB7F21 IO232NB7F21 IO232PB7F21 IO233NB7F21 IO233PB7F21 IO234NB7F21 IO234PB7F21 IO235NB7F21 IO235PB7F21 IO236NB7F22 IO237NB7F22 IO237PB7F22 IO238NB7F22 IO239NB7F22 IO239PB7F22 IO240NB7F22 IO241NB7F22 IO241PB7F22 IO242NB7F22 IO243NB7F22 IO243PB7F22 J2 J1 G2 H3 H2 K2 L2 K1 L1 E2 F2 F1 G1 L3 M3 D1 E1 K4 L4 M6 N8 N7 M5 L6 L5 M4 L7 M7 J3 M9 M8 Pin Number P4 M2 N2 N3 P3
624-Pin CCGA AX1000 Function IO244NB7F22 IO244PB7F22 IO245NB7F22 IO245PB7F22 IO246NB7F22 IO246PB7F22 IO247NB7F23 IO247PB7F23 IO248NB7F23 IO249NB7F23 IO249PB7F23 IO251NB7F23 IO251PB7F23 IO253NB7F23 IO253PB7F23 IO255NB7F23 IO255PB7F23 IO257NB7F23 IO257PB7F23 Dedicated I/O GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND K5 A18 A2 A24 A25 A8 AA10 AA16 AA18 AA21 AA5 AB22 AB4 AC10 AC16 AC23 AC3 Pin Number P9 N6 K8 L8 F3 E3 K7 K6 D2 G4 G3 N10 N9 H4 J4 J6 J5 H5 H6
3 -1 0 6
v2.7
Axcelerator Family FPGAs
624-Pin CCGA AX1000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND/LP GND GND GND GND GND GND GND GND GND GND GND GND Pin Number AD1 AD2 AD24 AD25 AE1 AE18 AE2 AE24 AE25 AE8 B1 B2 B24 B25 C10 C16 C23 C3 D22 D4 E10 E16 E21 E5 E8 H1 H21 H25 K21 K23 K3 L11 L12 L13 L14 L15 M11
624-Pin CCGA AX1000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC PRA PRB PRC PRD Pin Number M12 M13 M14 M15 N11 N12 N13 N14 N15 P11 P12 P13 P14 P15 R11 R12 R13 R14 R15 T21 T23 T3 T5 V1 V25 V5 A14 AA20 AB13 AD4 AE12 F21 G10 F13 A13 AB12 AE13
624-Pin CCGA AX1000 Function TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA Pin Number F5 C5 F6 D6 E6 AB20 F22 F4 J17 J9 K10 K11 K15 K16 L10 L16 R10 R16 T10 T11 T15 T16 U17 U9 Y4 A12 AA13 AA15 AA7 AC11 AD11 AE17 B15 C15 C6 D13 E13
v2.7
3-107
Axcelerator Family FPGAs
624-Pin CCGA AX1000 Function VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB4 Pin Number E19 G5 N21 N5 W21 A3 B3 C4 D5 J10 J11 K12 A23 B23 C22 D21 J15 J16 K14 C24 C25 D23 E22 K17 L17 M16 AA22 AB23 AC24 AC25 P16 R17 T17 AB21 AC22 AD23 AE23
624-Pin CCGA AX1000 Function VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE Pin Number T14 U15 U16 AB5 AC4 AD3 AE3 T12 U10 U11 AA4 AB3 AC1 AC2 P10 R9 T9 C1 C2 D3 E4 K9 L9 M10 E12 J12 E14 H14 Y14 U14 Y12 U12 F12 H12 F14 J14 AA14
624-Pin CCGA AX1000 Function VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number V14 AA12 V12 E20
3 -1 0 8
v2.7
Axcelerator Family FPGAs
624-Pin CCGA AX2000 Function Bank 0 IO00NB0F0 IO00PB0F0 IO01NB0F0 IO01PB0F0 IO02NB0F0 IO02PB0F0 IO04PB0F0 IO05NB0F0 IO05PB0F0 IO06NB0F0 IO06PB0F0 IO11NB0F0 IO11PB0F0 IO12PB0F1 IO13NB0F1 IO13PB0F1 IO15NB0F1 IO15PB0F1 IO16NB0F1 IO16PB0F1 IO17NB0F1 IO17PB0F1 IO18NB0F1 IO18PB0F1 IO19NB0F1 IO19PB0F1 IO20PB0F1 IO23NB0F2 IO23PB0F2 IO26NB0F2 IO26PB0F2 IO27NB0F2 IO27PB0F2 IO28NB0F2 IO28PB0F2 D7* E7* G7 G6 B5 B4 C7 F8 F7 H8 H7 J8 J7 B6 E9* D8* C9 C8 A5 A4 D10 D9 A7 A6 G9 G8 B7 F10 F9 C11* B8* H10 H9 A9 B9 Pin Number
624-Pin CCGA AX2000 Function IO30NB0F2 IO30PB0F2 IO31NB0F2 IO31PB0F2 IO33NB0F2 IO33PB0F2 IO34NB0F3 IO34PB0F3 IO37NB0F3 IO37PB0F3 IO38NB0F3 IO38PB0F3 IO40PB0F3 IO41NB0F3/HCLKAN IO41PB0F3/HCLKAP IO42NB0F3/HCLKBN IO42PB0F3/HCLKBP Bank 1 IO43NB1F4/HCLKCN IO43PB1F4/HCLKCP IO44NB1F4/HCLKDN IO44PB1F4/HCLKDP IO45NB1F4 IO47NB1F4 IO47PB1F4 IO48NB1F4 IO48PB1F4 IO49PB1F4 IO51NB1F4 IO51PB1F4 IO52NB1F4 IO55NB1F5 IO55PB1F5 IO56NB1F5 IO56PB1F5 IO57NB1F5 G15 G14 B14 B13 H13 D14 C14 A16 A15 H15 E15 F15 A17 G16 H16 A20 A19 D16 Pin Number B11 B10 E11 F11 D12 D11 A11 A10 J13 K13 H11 G11 B12 G13 G12 C13 C12
624-Pin CCGA AX2000 Function IO57PB1F5 IO58NB1F5 IO58PB1F5 IO59NB1F5 IO61NB1F5 IO61PB1F5 IO62NB1F5 IO62PB1F5 IO63NB1F5 IO65NB1F6 IO66PB1F6 IO67NB1F6 IO67PB1F6 IO68NB1F6 IO68PB1F6 IO69NB1F6 IO69PB1F6 IO70NB1F6 IO70PB1F6 IO71PB1F6 IO73NB1F6 IO74NB1F6 IO74PB1F6 IO75NB1F6 IO75PB1F6 IO76NB1F7 IO76PB1F7 IO79NB1F7 IO79PB1F7 IO80NB1F7 IO80PB1F7 IO81NB1F7 IO81PB1F7 IO82NB1F7 IO82PB1F7 IO85NB1F7 Pin Number D15 A22 A21 F16 G17 H17 B17 B16 H18 C17 B18 J18 J19 B20 B19 E17 F17 B22 B21 G18 G19 C19 C18 D18 D17 C21 C20 H20 H19 E18 F18 G21 G20 F20 F19 D20*
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
v2.7
3-109
Axcelerator Family FPGAs
624-Pin CCGA AX2000 Function IO85PB1F7 Bank 2 IO86NB2F8 IO86PB2F8 IO87NB2F8 IO87PB2F8 IO88NB2F8 IO88PB2F8 IO89NB2F8 IO89PB2F8 IO91NB2F8 IO91PB2F8 IO92NB2F8 IO92PB2F8 IO96NB2F9 IO96PB2F9 IO97NB2F9 IO97PB2F9 IO98PB2F9 IO99NB2F9 IO99PB2F9 IO100NB2F9 IO100PB2F9 IO103PB2F9 IO105NB2F9 IO105PB2F9 IO106NB2F9 IO106PB2F9 IO107NB2F10 IO107PB2F10 IO109NB2F10 IO109PB2F10 IO110NB2F10 IO110PB2F10 IO111NB2F10 IO111PB2F10 F23 E23 H23 G23 E24 D24 M17* G22* J22 H22 L18 K18 G24 F24 J21 J20 J23 L19 K19 E25 D25 K20 M19 M18 J24 H24 L23* N16* L22 K22 G25 F25 L21 L20 Pin Number D19*
624-Pin CCGA AX2000 Function IO112NB2F10 IO112PB2F10 IO113NB2F10 IO115NB2F10 IO115PB2F10 IO117NB2F10 IO117PB2F10 IO118NB2F11 IO121NB2F11 IO121PB2F11 IO122NB2F11 IO122PB2F11 IO123NB2F11 IO123PB2F11 IO124NB2F11 IO124PB2F11 IO127NB2F11 IO127PB2F11 IO128NB2F11 IO128PB2F11 Bank 3 IO129NB3F12 IO130PB3F12 IO131NB3F12 IO133NB3F12 IO133PB3F12 IO138NB3F12 IO138PB3F12 IO139NB3F13 IO139PB3F13 IO141NB3F13 IO142NB3F13 IO142PB3F13 IO143PB3F13 IO145NB3F13 IO145PB3F13 N20 P24 P21 P20 P19 R23 P23 R22 P22 R19 R25 P25 R21 T18 R18 Pin Number L24 K24 N17 M20 M21 N19 N18 J25 N24 M24 L25 K25 N22 M22 N23 M23 P18 P17 N25 M25
624-Pin CCGA AX2000 Function IO146NB3F13 IO146PB3F13 IO147NB3F13 IO147PB3F13 IO148NB3F13 IO148PB3F13 IO149NB3F13 IO153NB3F14 IO153PB3F14 IO154NB3F14 IO154PB3F14 IO157NB3F14 IO157PB3F14 IO158NB3F14 IO158PB3F14 IO160PB3F14 IO161NB3F15 IO161PB3F15 IO162NB3F15 IO162PB3F15 IO163NB3F15 IO163PB3F15 IO164NB3F15 IO164PB3F15 IO166NB3F15 IO167NB3F15 IO167PB3F15 IO168NB3F15 IO168PB3F15 IO169NB3F15 IO169PB3F15 IO170NB3F15 IO170PB3F15 Bank 4 IO171NB4F16 IO171PB4F16 AC20* AC21* Pin Number T24 R24 T20 R20 U25 T25 T22 U19 T19 Y25 W25 V20 U20 AB25 AA25 W24 U24 U23 AA24 Y24 V22 U22 V23 V24 AB24 V21 U21 Y23 AA23 W22* W23* Y22 Y21
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
3 -1 1 0
v2.7
Axcelerator Family FPGAs
624-Pin CCGA AX2000 Function IO172NB4F16 IO172PB4F16 IO173NB4F16 IO173PB4F16 IO174NB4F16 IO176NB4F16 IO176PB4F16 IO177NB4F16 IO177PB4F16 IO182NB4F17 IO182PB4F17 IO183PB4F17 IO184NB4F17 IO184PB4F17 IO185NB4F17 IO185PB4F17 IO187PB4F17 IO188NB4F17 IO188PB4F17 IO189PB4F17 IO191NB4F17 IO191PB4F17 IO192PB4F17 IO195PB4F18 IO196NB4F18 IO197NB4F18 IO197PB4F18 IO198NB4F18 IO198PB4F18 IO199NB4F18 IO199PB4F18 IO200NB4F18 IO201NB4F18 IO201PB4F18 IO202NB4F18 IO202PB4F18 Pin Number W20 Y20 AD21 AD22 AA19 Y18 Y19 AB19 AB18 V19 W19 AC19 AB17 AC17 AD19 AD20 AC18 Y17 AA17 AE22 W18 V18 U18 AE21 AB16 AD17 AD18 V17 W17 AE19 AE20 AC15 AD15 AD16 Y15 Y16
624-Pin CCGA AX2000 Function IO206NB4F19 IO206PB4F19 IO207NB4F19 IO207PB4F19 IO208PB4F19 IO209NB4F19 IO210NB4F19 IO210PB4F19 IO211NB4F19 IO211PB4F19 IO212NB4F19/CLKEN IO212PB4F19/CLKEP IO213NB4F19/CLKFN IO213PB4F19/CLKFP Bank 5 IO214NB5F20/CLKGN IO214PB5F20/CLKGP IO215NB5F20/CLKHN IO215PB5F20/CLKHP IO216NB5F20 IO216PB5F20 IO217NB5F20 IO217PB5F20 IO218NB5F20 IO218PB5F20 IO222NB5F20 IO222PB5F20 IO223PB5F21 IO225NB5F21 IO225PB5F21 IO226NB5F21 IO226PB5F21 IO227PB5F21 IO228NB5F21 IO228PB5F21 IO229NB5F21 W13 Y13 AC12 AD12 U13 V13 AE10 AE11 W11 W12 AA11 Y11 AE9 AE6 AE7 Y10 W10 T13 AB10 AB11 AD9 Pin Number AB14 AB15 AE15 AE16 W16 AE14 V15 V16 AD14 AC14 W14 W15 AC13 AD13
624-Pin CCGA AX2000 Function IO229PB5F21 IO230NB5F21 IO233NB5F21 IO233PB5F21 IO234NB5F21 IO234PB5F21 IO236NB5F22 IO238NB5F22 IO238PB5F22 IO239NB5F22 IO239PB5F22 IO240NB5F22 IO242NB5F22 IO242PB5F22 IO243NB5F22 IO243PB5F22 IO244NB5F22 IO246NB5F23 IO246PB5F23 IO247NB5F23 IO247PB5F23 IO250NB5F23 IO250PB5F23 IO251NB5F23 IO251PB5F23 IO252NB5F23 IO252PB5F23 IO253NB5F23 IO253PB5F23 IO254NB5F23 IO254PB5F23 IO256NB5F23 IO256PB5F23 Bank 6 IO257NB6F24 IO257PB6F24 Y3 AA3 Pin Number AD10 V11 AD7 AD8 V9 V10 AC9 W8 W9 AE4 AE5 AB9 AA9 Y9 AD5 AD6 U8 AB8 AC8 AB7 AC7 AA8 Y8 V8 V7 Y7 W7 AC5 AC6 Y6 W6 AB6* AA6*
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
v2.7
3-111
Axcelerator Family FPGAs
624-Pin CCGA AX2000 Function IO258NB6F24 IO258PB6F24 IO259NB6F24 IO259PB6F24 IO260NB6F24 IO260PB6F24 IO262NB6F24 IO262PB6F24 IO263NB6F24 IO263PB6F24 IO268NB6F25 IO268PB6F25 IO269PB6F25 IO272NB6F25 IO272PB6F25 IO273NB6F25 IO273PB6F25 IO274NB6F25 IO274PB6F25 IO275NB6F25 IO275PB6F25 IO277NB6F25 IO278NB6F26 IO278PB6F26 IO279PB6F26 IO280NB6F26 IO281NB6F26 IO281PB6F26 IO284NB6F26 IO284PB6F26 IO285NB6F26 IO285PB6F26 IO286NB6F26 IO286PB6F26 IO287NB6F26 IO287PB6F26 Pin Number V3 W3 AA2 AB2 V6* W4* U4 V4 Y5 W5 U6 U5 U3 T2 U2 W2 Y2 R6 T6 T7 U7 V2 R4 T4 R3 R5 AA1 AB1 R8 T8 W1 Y1 P2 R2 T1 U1
624-Pin CCGA AX2000 Function IO288NB6F26 IO290NB6F27 IO291NB6F27 IO291PB6F27 IO292NB6F27 IO292PB6F27 IO293NB6F27 IO293PB6F27 IO294NB6F27 IO296NB6F27 IO296PB6F27 IO298NB6F27 IO298PB6F27 IO299NB6F27 IO299PB6F27 Bank 7 IO300NB7F28 IO300PB7F28 IO302NB7F28 IO304NB7F28 IO304PB7F28 IO308NB7F28 IO309NB7F28 IO309PB7F28 IO310NB7F29 IO310PB7F29 IO311NB7F29 IO311PB7F29 IO313NB7F29 IO316NB7F29 IO316PB7F29 IO317NB7F29 IO317PB7F29 IO318NB7F29 IO318PB7F29 IO320NB7F29 P9* N6* M6 N8 N7 M4 L3 M3 N10 N9 K1 L1 M5 L6 L5 K2 L2 K4 L4 J3 Pin Number P5 P6 P1 R1 P7 R7 M1 N1 P8 N3 P3 N4 P4 M2 N2
624-Pin CCGA AX2000 Function IO321NB7F30 IO321PB7F30 IO323NB7F30 IO323PB7F30 IO324NB7F30 IO324PB7F30 IO327NB7F30 IO327PB7F30 IO328NB7F30 IO328PB7F30 IO329NB7F30 IO329PB7F30 IO331PB7F30 IO332NB7F31 IO332PB7F31 IO333NB7F31 IO333PB7F31 IO334NB7F31 IO334PB7F31 IO335NB7F31 IO335PB7F31 IO337NB7F31 IO338NB7F31 IO338PB7F31 IO339NB7F31 IO339PB7F31 IO340NB7F31 IO340PB7F31 IO341NB7F31 IO341PB7F31 Dedicated I/O GND GND GND GND GND K5 A18 A2 A24 A25 Pin Number J2 J1 L7 M7 M9 M8 F1 G1 K7 K6 D1 E1 G2 H3 H2 E2 F2 H4 J4 H5 H6 D2 J6 J5 F3 E3 G4* G3* K8 L8
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
3 -1 1 2
v2.7
Axcelerator Family FPGAs
624-Pin CCGA AX2000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number A8 AA10 AA16 AA18 AA21 AA5 AB22 AB4 AC10 AC16 AC23 AC3 AD1 AD2 AD24 AD25 AE1 AE18 AE2 AE24 AE25 AE8 B1 B2 B24 B25 C10 C16 C23 C3 D22 D4 E10 E16 E21 E5
624-Pin CCGA AX2000 Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Pin Number E8 H1 H21 H25 K21 K23 K3 L11 L12 L13 L14 L15 M11 M12 M13 M14 M15 N11 N12 N13 N14 N15 P11 P12 P13 P14 P15 R11 R12 R13 R14 R15 T21 T23 T3 T5
624-Pin CCGA AX2000 Function GND GND GND PRA PRB PRC PRD TCK TDI TDO TMS TRST VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCA VCCDA VCCDA VCCDA VCCDA Pin Number V1 V25 V5 F13 A13 AB12 AE13 F5 C5 F6 D6 E6 AB20 F22 F4 J17 J9 K10 K11 K15 K16 L10 L16 R10 R16 T10 T11 T15 T16 U17 U9 Y4 A12 A14 AA13 AA15
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
v2.7
3-113
Axcelerator Family FPGAs
624-Pin CCGA AX2000 Function VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCDA VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB2 VCCIB2 Pin Number AA20 AA7 AB13 AC11 AD11 AD4 AE12 AE17 B15 C15 C6 D13 E13 E19 F21 G10 G5 N21 N5 W21 A3 B3 C4 D5 J10 J11 K12 A23 B23 C22 D21 J15 J16 K14 C24 C25
624-Pin CCGA AX2000 Function VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB2 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB3 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB6 VCCIB7 VCCIB7 VCCIB7 Pin Number D23 E22 K17 L17 M16 AA22 AB23 AC24 AC25 P16 R17 T17 AB21 AC22 AD23 AE23 T14 U15 U16 AB5 AC4 AD3 AE3 T12 U10 U11 AA4 AB3 AC1 AC2 P10 R9 T9 C1 C2 D3
624-Pin CCGA AX2000 Function VCCIB7 VCCIB7 VCCIB7 VCCIB7 VCCPLA VCCPLB VCCPLC VCCPLD VCCPLE VCCPLF VCCPLG VCCPLH VCOMPLA VCOMPLB VCOMPLC VCOMPLD VCOMPLE VCOMPLF VCOMPLG VCOMPLH VPUMP Pin Number E4 K9 L9 M10 E12 J12 E14 H14 Y14 U14 Y12 U12 F12 H12 F14 J14 AA14 V14 AA12 V12 E20
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
* Not routed on the same package layer and to adjacent LGA pads as its differential pair complement. Recommended to be used as a single-ended I/O.
3 -1 1 4
v2.7
Axcelerator Family FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version v2.6 Changes in Current Version (v2.7) RoHS-compliant information was added to the "Ordering Information". ACTgen was changed to SmartGen because ACTgen was obsolete. v2.5 In Table 2-4, the units for the PLOAD, P10, and PI/O were updated from mW/MHz to mW/MHz. In the "Pin Descriptions"section, the HCLK and CLK descriptions were updated to include tie-off information. The "Global Resource Distribution" section was updated. The " 624-Pin CCGA" table was updated. v2.4 A note was added to Table 2-2. In the "Package Thermal Characteristics", the temperature was changed from 150C to 125C. v2.3 Revised ordering information and timing data to reflect phase out of -3 speed grade options. Table 2-3 was updated. v2.2 The "Packaging Data" section is new. Table 2-2 was updated. "VCCDA Supply Voltage" was updated. "PRA/B/C/D Probe A/B/C/D" was updated. The "User I/Os" was updated. v2.1 Figure 1-3 was updated. Table 2-2 was updated. The "Power-Up/Down Sequence" section was updated. Table 2-4 was updated. Table 2-5 was updated. The "Timing Characteristics" section was added. Table 2-7 was updated. Figure 2-1 was updated. The External Setup and Clock-to-Out (Pad-to-Pad) equations in the "Hardwired Clock - Using LVTTL 24mA High Slew Clock I/O" section were updated. The External Setup and Clock-to-Out (Pad-to-Pad) in the "Routed Clock - Using LVTTL 24mA High Slew Clock I/O" section were updated. The "Global Pins" section was updated. The "User I/Os" section was updated. Table 2-17 was updated. Figure 2-8 was updated. Figure 2-13 and Figure 2-14 were updated. 2 iii 2-1 2-9 2-10 2-10 1-3 2-1 2-1 2-2 2-3 2-7 2-7 2-8 2-8 2-8 2-9 2-10 2-17 2-18 2-21 Page ii N/A 2-2 2-9 2-59 3-103 2-1 2-6
v2.7
4-1
Axcelerator Family FPGAs
Previous Version v2.1 (continued)
Changes in Current Version (v2.7) The following timing parameters were renamed in I/O timing characteristic tables from Table 2-21 to Table 2-59: tIOCLKQ > tICLKQ tIOCLKY > tOCLKQ Timing numbers were updated from Table 2-21 to Table 2-77. The "R-Cell" section was updated. Figure 2-59 was updated. Figure 2-60 was updated. Figure 2-67 was updated. Figure 2-68 was updated. Table 2-88 to Table 2-92 were updated. Table 2-97 to Table 2-101 were updated. The "TRST" section was updated. The "Global Set Fuse" section was added. A footnote was added to "896-Pin FBGA" for the AX2000 regarding pins AB1, AE2, G1, and K2. Pinouts for the AX250, AX500 and AX1000 were added for "352-Pin CQFP". Pinout for the AX1000 was added for "624-Pin CCGA".
Page 2-22 to 2-41
2-22 to 2-58 2-47 2-74 2-75 2-85 2-86 2-75 to 2-79 2-86 to 2-88 2-89 2-90 3-49 3-88 3-102 2-58 2-89 i ii ii iii iii 2-11 2-11 2-1 2-1 2-2 2-2 2-3 2-5 2-6 2-6 2-7 2-9 2-22 to 2-48 2-55
v2.0
Table 2-78 was updated. The "Low Power Mode" section was updated.
Advanced v1.6
Table 1-1 has been updated. "Ordering Information" section has been updated. The "Device Resources" section has been updated. The "Temperature Grade Offerings" section is new. The "Speed Grade and Temperature Grade Matrix" section has been updated. Table 2-9 has been updated. Table 2-10 has been updated. Table 2-1 has been updated. Table 2-2 has been updated. Table 2-3 has been updated. Table 2-4 has been updated. Table 2-5 has been updated. The "Power Estimation Example" section has been updated. The "Thermal Characteristics" section has been updated. The "Package Thermal Characteristics" section has been updated. The "Timing Characteristics" section has been updated. The "Pin Descriptions" section has been updated. Timing numbers have been updated from the "3.3V LVTTL" section to the "Timing Characteristics" section. Many AC Loads were updated as well. Timing characteristics for the "Hardwired Clocks" section were updated.
4 -2
v2.7
Axcelerator Family FPGAs
Previous Version Advanced v0.6 (continued)
Changes in Current Version (v2.7) Timing characteristics for the "Routed Clocks" section were updated. Table 2-88 to Table 2-91 were updated. Table 2-97 to Table 2-98were updated. The "Low Power Mode" section was updated. The "Interface" section was updated. The "Data Registers (DRs)" section was updated. The "Security" section was updated. The "Silicon Explorer II Probe Interface" section was updated. The "Programming" section was updated. In the "208-Pin PQFP" (AX500) section, pins 2, 52, and 156 changed from VCCDA to VCCA. For pins 170 and 171, the I/O names refer to pair 23 instead of 24. The following changes were made in the "676-Pin FBGA"(AX500) section: AE2, AE25 Change from NC to GND. AF2, AF25 Changed from GND to NC AB4, AF24, C1, C26 Changed from VCCDA to VCCA AD15 Change from VCCDA to VCOMPLE AD17 Changed from VCOMPLE to VCCDA In the "896-Pin FBGA" (AX2000) section, the AK28 changed from VCCIB5 to VCCIB4. The "352-Pin CQFP" section is new. The "624-Pin CCGA" section is new.
Page 2-57 2-75 to 2-78 2-86 to 2-87 2-89 2-89 2-90 2-90 2-91 2-91 3-78 3-36
3-49 3-88 3-102 n/a i 1-7 2-14 2-14 3-22 2-2 2-8 2-63 2-68 3-78 3-22
Advanced v1.5
All I/O FIFO capability was removed. Table 1-1 was updated. Figure 1-9 and was updated. Figure 2-5 was updated. The "Using an I/O Register" section was updated. The AX250 and AX1000 descriptions were added to the "484-Pin FBGA"section.
Advanced v1.4
Table 2-3 was updated. Figure 2-1 was updated. Figure 2-48 was updated. Figure 2-52 was updated.
Advanced v1.3
In the "208-Pin PQFP" table, pin 196 was missing, but it has been added in this version with a function of GND. The following pins in the "484-Pin FBGA" table for AX500 were changed: Pin G7 is GND/LP Pins AB8, C10, C11, C14, AB16 are NC. The "676-Pin FBGA" table was updated.
3-36
v2.7
4-3
Axcelerator Family FPGAs
Previous Version Advanced v1.2
Changes in Current Version (v2.7) The "Device Resources" section was updated for the CS180. The "Programmable Interconnect Element" and Figure 1-2 was new. The "180-Pin CSP" table is new. The "208-Pin PQFP" tables for the AX500 were updated. The following pins were not defined in the previous version: GND 21 IO106PB5F10/CLKHP 71 GND 136
Page ii 1-1 and 1-2 3-1 3-78
Advanced v1.1
Table 1-1 was updated. "Ordering Information", "Device Resources" and the Product Plan table were updated. Figure 1-3 was updated. The "Design Environment" section was updated. Figure 1-8 was new. Table 2-3 was updated. "Package Thermal Characteristics" was updated. Figure 2-2 was updated. Table 2-8 was updated. Figure 2-11 was updated. The timing characteristics tables from pages 2-22 to 2-49 were updated. The "Global Resources" section was updated. The timing characteristics tables from pages 2-86 to 2-87 were updated. The "208-Pin PQFP" tables are new. The "256-Pin FBGA" tables are new. The "324-Pin FBGA" tables are new.
i ii 1-3 1-6 1-6 2-2 2-6 2-9 2-11 2-20 2-22 to 2-49 2-55 2-86 to 2-87 3-78 3-12 3-18
4 -4
v2.7
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Web-only." The definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a advanced datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this datasheet are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.
Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners.
w w w. a c t e l . c o m
Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. River Court, Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540 Actel Japan EXOS Ebisu Building 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 http://jp.actel.com Actel Hong Kong Room 2107, China Resources Building 26 Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 www.actel.com.cn
5172160-15/11.08

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